add trivial LD/ST redirectors into RADIX ISACaller

[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 2c0d0f4271ed2316fe11cf962e7168c20ad0e9b7..4063dac8d64a5457195dac7ec86bde5e8b766ed8 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -225,10 +225,13 @@ class RADIX:
 
         pte = self._walk_tree()
         # use pte to caclculate phys address
-        #mem.ld(address,width,swap,check_in_mem)
+        return self.mem.ld(address, width, swap, check_in_mem)
 
     # TODO implement
-    # def st(self, addr, v, width=8, swap=True):
+    def st(self, addr, v, width=8, swap=True):
+        # use pte to caclculate phys address (addr)
+        return self.mem.st(addr, v, width, swap)
+
     # def memassign(self, addr, sz, val):
     def _next_level(self):
         return True