add srcstep and correct PC-advancing during Sub-PC looping in ISACaller

[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index d8774b4c66d50c9dac2e0b36246196024340980a..4a38a1ede376a61c3402c20b46715dabfe4b92ce 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -20,9 +20,11 @@ from soc.decoder.orderedset import OrderedSet
 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
                                         selectconcat)
 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
                                         selectconcat)
 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,

-                                     insns, MicrOp)
+                                     insns, MicrOp, In1Sel, In2Sel, In3Sel,
+                                     OutSel)

 from soc.decoder.helpers import exts, gtu, ltu, undefined
 from soc.consts import PIb, MSRb  # big-endian (PowerISA versions)
 from soc.decoder.helpers import exts, gtu, ltu, undefined
 from soc.consts import PIb, MSRb  # big-endian (PowerISA versions)

+from soc.decoder.power_svp64 import SVP64RM, decode_extra

 
 from collections import namedtuple
 import math
 
 from collections import namedtuple
 import math


@@ -163,9 +165,11 @@ class Mem:
 
 
 class GPR(dict):
 
 
 class GPR(dict):

-    def __init__(self, decoder, regfile):
+    def __init__(self, decoder, isacaller, svstate, regfile):

         dict.__init__(self)
         self.sd = decoder
         dict.__init__(self)
         self.sd = decoder

+        self.isacaller = isacaller
+        self.svstate = svstate

         for i in range(32):
             self[i] = SelectableInt(regfile[i], 64)
 
         for i in range(32):
             self[i] = SelectableInt(regfile[i], 64)
 


@@ -188,8 +192,11 @@ class GPR(dict):
         return rnum
 
     def ___getitem__(self, attr):
         return rnum
 
     def ___getitem__(self, attr):

-        print("GPR getitem", attr)
+        """ XXX currently not used
+        """

         rnum = self._get_regnum(attr)
         rnum = self._get_regnum(attr)

+        offs = self.svstate.srcstep
+        print("GPR getitem", attr, rnum, "srcoffs", offs)

         return self.regfile[rnum]
 
     def dump(self):
         return self.regfile[rnum]
 
     def dump(self):


@@ -204,11 +211,17 @@ class GPR(dict):
 class PC:
     def __init__(self, pc_init=0):
         self.CIA = SelectableInt(pc_init, 64)
 class PC:
     def __init__(self, pc_init=0):
         self.CIA = SelectableInt(pc_init, 64)

-        self.NIA = self.CIA + SelectableInt(4, 64)
+        self.NIA = self.CIA + SelectableInt(4, 64) # only true for v3.0B!
+
+    def update_nia(self, is_svp64):
+        increment = 8 if is_svp64 else 4
+        self.NIA = self.CIA + SelectableInt(increment, 64)

 
 

-    def update(self, namespace):
+    def update(self, namespace, is_svp64):
+        """updates the program counter (PC) by 4 if v3.0B mode or 8 if SVP64
+        """

         self.CIA = namespace['NIA'].narrow(64)
         self.CIA = namespace['NIA'].narrow(64)

-        self.NIA = self.CIA + SelectableInt(4, 64)
+        self.update_nia(is_svp64)

         namespace['CIA'] = self.CIA
         namespace['NIA'] = self.NIA
 
         namespace['CIA'] = self.CIA
         namespace['NIA'] = self.NIA
 


@@ -309,6 +322,68 @@ class SPR(dict):
     def __call__(self, ridx):
         return self[ridx]
 
     def __call__(self, ridx):
         return self[ridx]
 

+def get_pdecode_idx_in(dec2, name):
+    op = dec2.dec.op
+    in1_sel = yield op.in1_sel
+    in2_sel = yield op.in2_sel
+    in3_sel = yield op.in3_sel
+    # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
+    in1 = yield dec2.e.read_reg1.data
+    in2 = yield dec2.e.read_reg2.data
+    in3 = yield dec2.e.read_reg3.data
+    in1_isvec = yield dec2.in1_isvec
+    in2_isvec = yield dec2.in2_isvec
+    in3_isvec = yield dec2.in3_isvec
+    print ("get_pdecode_idx", in1_sel, In1Sel.RA.value, in1, in1_isvec)
+    # identify which regnames map to in1/2/3
+    if name == 'RA':
+        if (in1_sel == In1Sel.RA.value or
+            (in1_sel == In1Sel.RA_OR_ZERO.value and in1 != 0)):
+            return in1, in1_isvec
+        if in1_sel == In1Sel.RA_OR_ZERO.value:
+            return in1, in1_isvec
+    elif name == 'RB':
+        if in2_sel == In2Sel.RB.value:
+            return in2, in2_isvec
+        if in3_sel == In3Sel.RB.value:
+            return in3, in3_isvec
+    # XXX TODO, RC doesn't exist yet!
+    elif name == 'RC':
+        assert False, "RC does not exist yet"
+    elif name == 'RS':
+        if in1_sel == In1Sel.RS.value:
+            return in1, in1_isvec
+        if in2_sel == In2Sel.RS.value:
+            return in2, in2_isvec
+        if in3_sel == In3Sel.RS.value:
+            return in3, in3_isvec
+    return None, False
+
+
+def get_pdecode_idx_out(dec2, name):
+    op = dec2.dec.op
+    out_sel = yield op.out_sel
+    # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
+    out = yield dec2.e.write_reg.data
+    o_isvec = yield dec2.o_isvec
+    print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
+    # identify which regnames map to out / o2
+    if name == 'RA':
+        if out_sel == OutSel.RA.value:
+            return out, o_isvec
+    elif name == 'RT':
+        if out_sel == OutSel.RT.value:
+            return out, o_isvec
+    print ("get_pdecode_idx_out not found", name)
+    return None, False
+
+
+# XXX TODO
+def get_pdecode_idx_out2(dec2, name):
+    op = dec2.dec.op
+    print ("TODO: get_pdecode_idx_out2", name)
+    return None, False
+

 
 class ISACaller:
     # decoder2 - an instance of power_decoder2
 
 class ISACaller:
     # decoder2 - an instance of power_decoder2


@@ -355,11 +430,14 @@ class ISACaller:
                 self.disassembly[i*4 + disasm_start] = code
 
         # set up registers, instruction memory, data memory, PC, SPRs, MSR
                 self.disassembly[i*4 + disasm_start] = code
 
         # set up registers, instruction memory, data memory, PC, SPRs, MSR

-        self.gpr = GPR(decoder2, regfile)
+        self.svp64rm = SVP64RM()
+        if isinstance(initial_svstate, int):
+            initial_svstate = SVP64State(initial_svstate)
+        self.svstate = initial_svstate
+        self.gpr = GPR(decoder2, self, self.svstate, regfile)

         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
         self.pc = PC()
         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
         self.pc = PC()

-        self.svstate = SVP64State(initial_svstate)

         self.spr = SPR(decoder2, initial_sprs)
         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
 
         self.spr = SPR(decoder2, initial_sprs)
         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
 


@@ -587,7 +665,7 @@ class ISACaller:
 
     def set_pc(self, pc_val):
         self.namespace['NIA'] = SelectableInt(pc_val, 64)
 
     def set_pc(self, pc_val):
         self.namespace['NIA'] = SelectableInt(pc_val, 64)

-        self.pc.update(self.namespace)
+        self.pc.update(self.namespace, self.is_svp64_mode)

 
     def setup_one(self):
         """set up one instruction
 
     def setup_one(self):
         """set up one instruction


@@ -603,6 +681,7 @@ class ISACaller:
         print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
         print("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
 
         print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
         print("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
 

+        yield self.dec2.sv_rm.eq(0)

         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
         yield self.dec2.dec.bigendian.eq(self.bigendian)
         yield self.dec2.state.msr.eq(self.msr.value)
         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
         yield self.dec2.dec.bigendian.eq(self.bigendian)
         yield self.dec2.state.msr.eq(self.msr.value)


@@ -611,7 +690,7 @@ class ISACaller:
         # SVP64.  first, check if the opcode is EXT001, and SVP64 id bits set
         yield Settle()
         opcode = yield self.dec2.dec.opcode_in
         # SVP64.  first, check if the opcode is EXT001, and SVP64 id bits set
         yield Settle()
         opcode = yield self.dec2.dec.opcode_in

-        pfx = SVP64PrefixFields()
+        pfx = SVP64PrefixFields() # TODO should probably use SVP64PrefixDecoder

         pfx.insn.value = opcode
         major = pfx.major.asint(msb0=True) # MSB0 inversion
         print ("prefix test: opcode:", major, bin(major),
         pfx.insn.value = opcode
         major = pfx.major.asint(msb0=True) # MSB0 inversion
         print ("prefix test: opcode:", major, bin(major),


@@ -619,14 +698,19 @@ class ISACaller:
         self.is_svp64_mode = ((major == 0b000001) and
                               pfx.insn[7].value == 0b1 and
                               pfx.insn[9].value == 0b1)
         self.is_svp64_mode = ((major == 0b000001) and
                               pfx.insn[7].value == 0b1 and
                               pfx.insn[9].value == 0b1)

+        self.pc.update_nia(self.is_svp64_mode)

         if not self.is_svp64_mode:
             return
 
         # in SVP64 mode.  decode/print out svp64 prefix, get v3.0B instruction
         print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
         if not self.is_svp64_mode:
             return
 
         # in SVP64 mode.  decode/print out svp64 prefix, get v3.0B instruction
         print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))

+        print ("    svstate.vl", self.svstate.vl.asint(msb0=True))
+        print ("    svstate.mvl", self.svstate.maxvl.asint(msb0=True))
+        sv_rm = pfx.rm.asint()

         ins = self.imem.ld(pc+4, 4, False, True)
         print("     svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
         ins = self.imem.ld(pc+4, 4, False, True)
         print("     svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))

-        yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
+        yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix
+        yield self.dec2.sv_rm.eq(sv_rm)                        # svp64 prefix

         yield Settle()
 
     def execute_one(self):
         yield Settle()
 
     def execute_one(self):


@@ -642,8 +726,10 @@ class ISACaller:
         opname = code.split(' ')[0]
         yield from self.call(opname)
 
         opname = code.split(' ')[0]
         yield from self.call(opname)
 

+        # don't use this except in special circumstances

         if not self.respect_pc:
             self.fake_pc += 4
         if not self.respect_pc:
             self.fake_pc += 4

+

         print("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value)
 
     def get_assembly_name(self):
         print("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value)
 
     def get_assembly_name(self):


@@ -709,6 +795,8 @@ class ISACaller:
         return dec_insn & (1 << 20) != 0  # sigh - XFF.spr[-1]?
 
     def call(self, name):
         return dec_insn & (1 << 20) != 0  # sigh - XFF.spr[-1]?
 
     def call(self, name):

+        """call(opcode) - the primary execution point for instructions
+        """

         name = name.strip()  # remove spaces if not already done so
         if self.halted:
             print("halted - not executing", name)
         name = name.strip()  # remove spaces if not already done so
         if self.halted:
             print("halted - not executing", name)


@@ -741,7 +829,7 @@ class ISACaller:
         if instr_is_privileged and self.msr[MSRb.PR] == 1:
             self.TRAP(0x700, PIb.PRIV)
             self.namespace['NIA'] = self.trap_nia
         if instr_is_privileged and self.msr[MSRb.PR] == 1:
             self.TRAP(0x700, PIb.PRIV)
             self.namespace['NIA'] = self.trap_nia

-            self.pc.update(self.namespace)
+            self.pc.update(self.namespace, self.is_svp64_mode)

             return
 
         # check halted condition
             return
 
         # check halted condition


@@ -758,7 +846,7 @@ class ISACaller:
             print("illegal", name, asmop)
             self.TRAP(0x700, PIb.ILLEG)
             self.namespace['NIA'] = self.trap_nia
             print("illegal", name, asmop)
             self.TRAP(0x700, PIb.ILLEG)
             self.namespace['NIA'] = self.trap_nia

-            self.pc.update(self.namespace)
+            self.pc.update(self.namespace, self.is_svp64_mode)

             print("name %s != %s - calling ILLEGAL trap, PC: %x" %
                   (name, asmop, self.pc.CIA.value))
             return
             print("name %s != %s - calling ILLEGAL trap, PC: %x" %
                   (name, asmop, self.pc.CIA.value))
             return


@@ -771,14 +859,37 @@ class ISACaller:
                                   list(info.uninit_regs))
         print(input_names)
 
                                   list(info.uninit_regs))
         print(input_names)
 

-        # main registers (RT, RA ...)
+        # get SVP64 entry for the current instruction
+        sv_rm = self.svp64rm.instrs.get(name)
+        if sv_rm is not None:
+            dest_cr, src_cr, src_byname, dest_byname = decode_extra(sv_rm)
+        else:
+            dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
+        print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
+
+        # get SVSTATE srcstep.  TODO: dststep (twin predication)
+        srcstep = self.svstate.srcstep.asint(msb0=True)
+
+        # main input registers (RT, RA ...)

         inputs = []
         for name in input_names:
         inputs = []
         for name in input_names:

-            regnum = yield getattr(self.decoder, name)
+            # using PowerDecoder2, first, find the decoder index.
+            # (mapping name RA RB RC RS to in1, in2, in3)
+            regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)
+            if regnum is None:
+                # doing this is not part of svp64, it's because output
+                # registers, to be modified, need to be in the namespace.
+                regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
+            # here's where we go "vector".  TODO: zero-testing (RA_IS_ZERO)
+            if is_vec:
+                regnum += srcstep # TODO, elwidth overrides
+
+            # in case getting the register number is needed, _RA, _RB

             regname = "_" + name
             self.namespace[regname] = regnum
             regname = "_" + name
             self.namespace[regname] = regnum

-            print('reading reg %d' % regnum)
-            inputs.append(self.gpr(regnum))
+            print('reading reg %s %d' % (name, regnum), is_vec)
+            reg_val = self.gpr(regnum)
+            inputs.append(reg_val)

 
         # "special" registers
         for special in info.special_regs:
 
         # "special" registers
         for special in info.special_regs:


@@ -843,6 +954,9 @@ class ISACaller:
         if rc_en:
             self.handle_comparison(results)
 
         if rc_en:
             self.handle_comparison(results)
 

+        # svp64 loop can end early if the dest is scalar
+        svp64_dest_vector = False
+

         # any modified return results?
         if info.write_regs:
             for name, output in zip(output_names, results):
         # any modified return results?
         if info.write_regs:
             for name, output in zip(output_names, results):


@@ -865,15 +979,48 @@ class ISACaller:
                     if name == 'MSR':
                         print('msr written', hex(self.msr.value))
                 else:
                     if name == 'MSR':
                         print('msr written', hex(self.msr.value))
                 else:

-                    regnum = yield getattr(self.decoder, name)
-                    print('writing reg %d %s' % (regnum, str(output)))
+                    regnum, is_vec = yield from get_pdecode_idx_out(self.dec2,
+                                                name)
+                    if regnum is None:
+                        # temporary hack for not having 2nd output
+                        regnum = yield getattr(self.decoder, name)
+                        is_vec = False
+                    # here's where we go "vector".
+                    if is_vec:
+                        regnum += srcstep # TODO, elwidth overrides
+                        svp64_dest_vector = True
+                    print('writing reg %d %s' % (regnum, str(output)), is_vec)

                     if output.bits > 64:
                         output = SelectableInt(output.value, 64)
                     self.gpr[regnum] = output
 
                     if output.bits > 64:
                         output = SelectableInt(output.value, 64)
                     self.gpr[regnum] = output
 

-        print("end of call", self.namespace['CIA'], self.namespace['NIA'])
+        # check if it is the SVSTATE.src/dest step that needs incrementing
+        # this is our Sub-Program-Counter loop from 0 to VL-1
+        if self.is_svp64_mode:
+            # XXX twin predication TODO
+            vl = self.svstate.vl.asint(msb0=True)
+            mvl = self.svstate.maxvl.asint(msb0=True)
+            srcstep = self.svstate.srcstep.asint(msb0=True)
+            print ("    svstate.vl", vl)
+            print ("    svstate.mvl", mvl)
+            print ("    svstate.srcstep", srcstep)
+            # check if srcstep needs incrementing by one, stop PC advancing
+            if svp64_dest_vector and srcstep != vl-1:
+                self.svstate.srcstep += SelectableInt(1, 7)
+                self.pc.NIA.value = self.pc.CIA.value
+                self.namespace['NIA'] = self.pc.NIA
+                print("end of sub-pc call", self.namespace['CIA'],
+                                     self.namespace['NIA'])
+                return # DO NOT allow PC to update whilst Sub-PC loop running
+            # reset to zero
+            self.svstate.srcstep[0:7] = 0
+            print ("    svstate.srcstep loop end (PC to update)")
+            self.pc.update_nia(self.is_svp64_mode)
+            self.namespace['NIA'] = self.pc.NIA
+

         # UPDATE program counter
         # UPDATE program counter

-        self.pc.update(self.namespace)
+        self.pc.update(self.namespace, self.is_svp64_mode)
+        print("end of call", self.namespace['CIA'], self.namespace['NIA'])

 
 
 def inject():
 
 
 def inject():