+ self.spr['SRR1'][63-trap_bit] = 1 # change *copy* of MSR in SRR1
+
+ # set exception bits. TODO: this should, based on the address
+ # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
+ # bits appropriately. however it turns out that *for now* in all
+ # cases (all trap_addrs) the exact same thing is needed.
+ self.namespace['MSR'][63-MSR.SF] = 1
+ self.namespace['MSR'][63-MSR.EE] = 0
+ self.namespace['MSR'][63-MSR.PR] = 0
+ self.namespace['MSR'][63-MSR.IR] = 0
+ self.namespace['MSR'][63-MSR.DR] = 0
+ self.namespace['MSR'][63-MSR.RI] = 0
+ self.namespace['MSR'][63-MSR.LE] = 1