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[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 0a94fff9927db6dfc1e3a708539a80f7fa014030..7ade13afd13381ab3df36fde8343973e39d0fbc3 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -687,7 +687,7 @@ class ISACaller:
         # SVP64.  first, check if the opcode is EXT001, and SVP64 id bits set
         yield Settle()
         opcode = yield self.dec2.dec.opcode_in
-        pfx = SVP64PrefixFields()
+        pfx = SVP64PrefixFields() # TODO should probably use SVP64PrefixDecoder
         pfx.insn.value = opcode
         major = pfx.major.asint(msb0=True) # MSB0 inversion
         print ("prefix test: opcode:", major, bin(major),
@@ -977,6 +977,25 @@ class ISACaller:
                     self.gpr[regnum] = output
 
         print("end of call", self.namespace['CIA'], self.namespace['NIA'])
+
+        # check if it is the SVSTATE.src/dest step that needs incrementing
+        # this is our Sub-Program-Counter loop from 0 to VL-1
+        if self.is_svp64_mode:
+            # XXX twin predication TODO
+            vl = self.svstate.vl.asint(msb0=True)
+            mvl = self.svstate.maxvl.asint(msb0=True)
+            srcstep = self.svstate.srcstep.asint(msb0=True)
+            print ("    svstate.vl", vl)
+            print ("    svstate.mvl", mvl)
+            print ("    svstate.srcstep", srcstep)
+            # check if srcstep needs incrementing by one
+            if srcstep != vl-1:
+                self.svstate.srcstep += SelectableInt(1, 7)
+                return # DO NOT allow PC to update whilst Sub-PC loop running
+            # reset to zero
+            self.svstate.srcstep[0:7] = 0
+            print ("    svstate.srcstep loop end (PC to update)")
+
         # UPDATE program counter
         self.pc.update(self.namespace, self.is_svp64_mode)