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simplify create_args
[soc.git] / src / soc / decoder / isa / caller.py
diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 293c81c655318931442118e2ed3785a36a16a137..9252bfef12369e1851d01abd47886de68a177f5e 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -41,14 +41,31 @@ def swap_order(x, nbytes):
     return x
 
 
+REG_SORT_ORDER = {
+    # TODO (lkcl): adjust other registers that should be in a particular order
+    # probably CA, CA32, and CR
+    "RT": 0,
+    "RA": 0,
+    "RB": 0,
+    "RS": 0,
+    "CR": 0,
+    "LR": 0,
+    "CTR": 0,
+    "TAR": 0,
+    "CA": 0,
+    "CA32": 0,
+    "MSR": 0,
+
+    "overflow": 1,
+}
+
+
 def create_args(reglist, extra=None):
-    args = OrderedSet()
-    for reg in reglist:
-        args.add(reg)
-    args = list(args)
-    if extra:
-        args = [extra] + args
-    return args
+    retval = list(OrderedSet(reglist))
+    retval.sort(key=lambda reg: REG_SORT_ORDER[reg])
+    if extra is not None:
+        return [extra] + retval
+    return retval
 
 
 class Mem:
@@ -216,9 +233,9 @@ class SPR(dict):
         if isinstance(key, int):
             key = spr_dict[key].SPR
         key = special_sprs.get(key, key)
-        if key == 'HSRR0': # HACK!
+        if key == 'HSRR0':  # HACK!
             key = 'SRR0'
-        if key == 'HSRR1': # HACK!
+        if key == 'HSRR1':  # HACK!
             key = 'SRR1'
         if key in self:
             res = dict.__getitem__(self, key)
@@ -239,9 +256,9 @@ class SPR(dict):
             key = spr_dict[key].SPR
             print("spr key", key)
         key = special_sprs.get(key, key)
-        if key == 'HSRR0': # HACK!
+        if key == 'HSRR0':  # HACK!
             self.__setitem__('SRR0', value)
-        if key == 'HSRR1': # HACK!
+        if key == 'HSRR1':  # HACK!
             self.__setitem__('SRR1', value)
         print("setting spr", key, value)
         dict.__setitem__(self, key, value)
@@ -431,7 +448,7 @@ class ISACaller:
             gts.append(gt)
         print(gts)
         cy = 1 if any(gts) else 0
-        print ("CA", cy, gts)
+        print("CA", cy, gts)
         if not (1 & already_done):
             self.spr['XER'][XER_bits['CA']] = cy
 
@@ -440,14 +457,14 @@ class ISACaller:
         # ARGH... different for OP_ADD... *sigh*...
         op = yield self.dec2.e.do.insn_type
         if op == MicrOp.OP_ADD.value:
-            res32 = (output.value & (1<<32)) != 0
-            a32 = (inputs[0].value & (1<<32)) != 0
+            res32 = (output.value & (1 << 32)) != 0
+            a32 = (inputs[0].value & (1 << 32)) != 0
             if len(inputs) >= 2:
-                b32 = (inputs[1].value & (1<<32)) != 0
+                b32 = (inputs[1].value & (1 << 32)) != 0
             else:
                 b32 = False
             cy32 = res32 ^ a32 ^ b32
-            print ("CA32 ADD", cy32)
+            print("CA32 ADD", cy32)
         else:
             gts = []
             for x in inputs:
@@ -457,14 +474,15 @@ class ISACaller:
                 gt = (gtu(x[32:64], output[32:64])) == SelectableInt(1, 1)
                 gts.append(gt)
             cy32 = 1 if any(gts) else 0
-            print ("CA32", cy32, gts)
+            print("CA32", cy32, gts)
         if not (2 & already_done):
             self.spr['XER'][XER_bits['CA32']] = cy32
 
     def handle_overflow(self, inputs, outputs, div_overflow):
-        inv_a = yield self.dec2.e.do.invert_in
-        if inv_a:
-            inputs[0] = ~inputs[0]
+        if hasattr(self.dec2.e.do, "invert_in"):
+            inv_a = yield self.dec2.e.do.invert_in
+            if inv_a:
+                inputs[0] = ~inputs[0]
 
         imm_ok = yield self.dec2.e.do.imm_data.ok
         if imm_ok:
@@ -504,7 +522,7 @@ class ISACaller:
     def handle_comparison(self, outputs):
         out = outputs[0]
         assert isinstance(out, SelectableInt), \
-                          "out zero not a SelectableInt %s" % repr(outputs)
+            "out zero not a SelectableInt %s" % repr(outputs)
         print("handle_comparison", out.bits, hex(out.value))
         # TODO - XXX *processor* in 32-bit mode
         # https://bugs.libre-soc.org/show_bug.cgi?id=424
@@ -567,19 +585,27 @@ class ISACaller:
         int_op = yield self.dec2.dec.op.internal_op
 
         # sigh reconstruct the assembly instruction name
-        ov_en = yield self.dec2.e.do.oe.oe
-        ov_ok = yield self.dec2.e.do.oe.ok
-        rc_en = yield self.dec2.e.do.rc.rc
-        rc_ok = yield self.dec2.e.do.rc.ok
+        if hasattr(self.dec2.e.do, "oe"):
+            ov_en = yield self.dec2.e.do.oe.oe
+            ov_ok = yield self.dec2.e.do.oe.ok
+        else:
+            ov_en = False
+            ov_ok = False
+        if hasattr(self.dec2.e.do, "rc"):
+            rc_en = yield self.dec2.e.do.rc.rc
+            rc_ok = yield self.dec2.e.do.rc.ok
+        else:
+            rc_en = False
+            rc_ok = False
         # grrrr have to special-case MUL op (see DecodeOE)
-        print("ov %d en %d rc %d en %d op %d" % \
-                        (ov_ok, ov_en, rc_ok, rc_en, int_op))
+        print("ov %d en %d rc %d en %d op %d" %
+              (ov_ok, ov_en, rc_ok, rc_en, int_op))
         if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]:
             print("mul op")
             if rc_en & rc_ok:
                 asmop += "."
         else:
-            if not asmop.endswith("."): # don't add "." to "andis."
+            if not asmop.endswith("."):  # don't add "." to "andis."
                 if rc_en & rc_ok:
                     asmop += "."
         if hasattr(self.dec2.e.do, "lk"):
@@ -658,7 +684,7 @@ class ISACaller:
             illegal = name != asmop
 
         if illegal:
-            print ("illegal", name, asmop)
+            print("illegal", name, asmop)
             self.TRAP(0x700, PIb.ILLEG)
             self.namespace['NIA'] = self.trap_nia
             self.pc.update(self.namespace)
@@ -715,7 +741,10 @@ class ISACaller:
                     already_done |= 2
 
         print("carry already done?", bin(already_done))
-        carry_en = yield self.dec2.e.do.output_carry
+        if hasattr(self.dec2.e.do, "output_carry"):
+            carry_en = yield self.dec2.e.do.output_carry
+        else:
+            carry_en = False
         if carry_en:
             yield from self.handle_carry_(inputs, results, already_done)
 
@@ -726,13 +755,20 @@ class ISACaller:
                 if name == 'overflow':
                     overflow = output
 
-        ov_en = yield self.dec2.e.do.oe.oe
-        ov_ok = yield self.dec2.e.do.oe.ok
+        if hasattr(self.dec2.e.do, "oe"):
+            ov_en = yield self.dec2.e.do.oe.oe
+            ov_ok = yield self.dec2.e.do.oe.ok
+        else:
+            ov_en = False
+            ov_ok = False
         print("internal overflow", overflow, ov_en, ov_ok)
         if ov_en & ov_ok:
             yield from self.handle_overflow(inputs, results, overflow)
 
-        rc_en = yield self.dec2.e.do.rc.rc
+        if hasattr(self.dec2.e.do, "rc"):
+            rc_en = yield self.dec2.e.do.rc.rc
+        else:
+            rc_en = False
         if rc_en:
             self.handle_comparison(results)