get fu compunit test to use ISACaller instruction-memory

[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 504ab94a69e4960184a925e24e707f2de5e923d0..c62a32c3416e0522615387ea481ebb11de8e4efe 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -226,6 +226,7 @@ class ISACaller:
             initial_insns = {}
             assert self.respect_pc == False, "instructions required to honor pc"
 
+        print ("ISACaller insns", respect_pc, initial_insns, disassembly)
 
         # "fake program counter" mode (for unit testing)
         if not respect_pc:
@@ -240,12 +241,14 @@ class ISACaller:
             for i, code in enumerate(disassembly):
                 self.disassembly[i*4 + self.fake_pc] = code
 
+        # set up registers, instruction memory, data memory, PC, SPRs, MSR
         self.gpr = GPR(decoder2, regfile)
         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
         self.pc = PC()
         self.spr = SPR(decoder2, initial_sprs)
         self.msr = SelectableInt(initial_msr, 64) # underlying reg
+
         # TODO, needed here:
         # FPR (same as GPR except for FP nums)
         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
@@ -391,17 +394,31 @@ class ISACaller:
         self.namespace['NIA'] = SelectableInt(pc_val, 64)
         self.pc.update(self.namespace)
 
-    def execute_one(self):
+    def setup_one(self):
+        """set up one instruction
+        """
         if self.respect_pc:
             pc = self.pc.CIA.value
         else:
             pc = self.fake_pc
-            self.fake_pc += 4
-        ins = yield self.imem.ld(pc, 4, False)
-        yield self.pdecode2.dec.raw_opcode_in.eq(ins)
-        yield self.pdecode2.dec.bigendian.eq(0)  # little / big?
+        self._pc = pc
+        ins = self.imem.ld(pc, 4, False)
+        print("setup: 0x{:X} 0x{:X}".format(pc, ins & 0xffffffff))
+
+        yield self.dec2.dec.raw_opcode_in.eq(ins)
+        yield self.dec2.dec.bigendian.eq(0)  # little / big?
+
+    def execute_one(self):
+        """execute one instruction
+        """
+        # get the disassembly code for this instruction
+        code = self.disassembly[self._pc]
+        print("sim-execute", hex(self._pc), code)
         opname = code.split(' ')[0]
-        yield from call(opname)
+        yield from self.call(opname)
+
+        if not self.respect_pc:
+            self.fake_pc += 4
 
     def call(self, name):
         # TODO, asmregs is from the spec, e.g. add RT,RA,RB