tracked down byte-reversal in LDST ISACaller and LDSTCompUnit

[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index c7d0784f04eb4c3cb2591a895f52a9494cf4e1ce..c8b5f4de151cfa8f6c9f64668a583fb9bae1b6db 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -112,8 +112,8 @@ class Mem:
         staddr = addr
         remainder = addr & (self.bytes_per_word - 1)
         addr = addr >> self.word_log2
-        print("Writing 0x{:x} to ST 0x{:x} memaddr 0x{:x}/{:x}".format(v,
-                                                                       staddr, addr, remainder, swap))
+        print("Writing 0x{:x} to ST 0x{:x} "
+              "memaddr 0x{:x}/{:x}".format(v, staddr, addr, remainder, swap))
         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
         if swap:
             v = swap_order(v, width)
@@ -131,13 +131,13 @@ class Mem:
         print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
 
     def __call__(self, addr, sz):
-        val = self.ld(addr.value, sz)
+        val = self.ld(addr.value, sz, swap=False)
         print("memread", addr, sz, val)
         return SelectableInt(val, sz*8)
 
     def memassign(self, addr, sz, val):
         print("memassign", addr, sz, val)
-        self.st(addr.value, val.value, sz)
+        self.st(addr.value, val.value, sz, swap=False)
 
 
 class GPR(dict):
@@ -513,8 +513,8 @@ class ISACaller:
 
         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
         yield self.dec2.dec.bigendian.eq(self.bigendian)
-        yield self.dec2.msr.eq(self.msr.value)
-        yield self.dec2.cia.eq(pc)
+        yield self.dec2.state.msr.eq(self.msr.value)
+        yield self.dec2.state.pc.eq(pc)
 
     def execute_one(self):
         """execute one instruction
@@ -532,8 +532,9 @@ class ISACaller:
     def get_assembly_name(self):
         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
+        dec_insn = yield self.dec2.e.do.insn
         asmcode = yield self.dec2.dec.op.asmcode
-        print("get assembly name asmcode", asmcode)
+        print("get assembly name asmcode", asmcode, hex(dec_insn))
         asmop = insns.get(asmcode, None)
         int_op = yield self.dec2.dec.op.internal_op
 
@@ -543,14 +544,16 @@ class ISACaller:
         rc_en = yield self.dec2.e.do.rc.data
         rc_ok = yield self.dec2.e.do.rc.ok
         # grrrr have to special-case MUL op (see DecodeOE)
-        print("ov en rc en", ov_ok, ov_en, rc_ok, rc_en, int_op)
+        print("ov %d en %d rc %d en %d op %d" % \
+                        (ov_ok, ov_en, rc_ok, rc_en, int_op))
         if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]:
             print("mul op")
             if rc_en & rc_ok:
                 asmop += "."
         else:
-            if ov_en & ov_ok:
-                asmop += "."
+            if not asmop.endswith("."): # don't add "." to "andis."
+                if rc_en & rc_ok:
+                    asmop += "."
         lk = yield self.dec2.e.do.lk
         if lk:
             asmop += "l"
@@ -626,6 +629,7 @@ class ISACaller:
             illegal = name != asmop
 
         if illegal:
+            print ("illegal", name, asmop)
             self.TRAP(0x700, PIb.ILLEG)
             self.namespace['NIA'] = self.trap_nia
             self.pc.update(self.namespace)