add SVSTATE SPR sub-field accessor class to ISACaller

[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 9252bfef12369e1851d01abd47886de68a177f5e..dfd69339de63f6d44f48f7ee4bc8d9ac2c92a201 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -16,7 +16,7 @@ from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
                                         selectconcat)
 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
                                      insns, MicrOp)
-from soc.decoder.helpers import exts, gtu, ltu
+from soc.decoder.helpers import exts, gtu, ltu, undefined
 from soc.consts import PIb, MSRb  # big-endian (PowerISA versions)
 
 from collections import namedtuple
@@ -208,6 +208,21 @@ class PC:
         namespace['NIA'] = self.NIA
 
 
+# Simple-V: see https://libre-soc.org/openpower/sv
+# also soc.sv.svp64 SVP64Rec
+class SVSTATE:
+    def __init__(self, init=0):
+        self.spr = SelectableInt(init, 32)
+        # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
+        self.mmode = FieldSelectableInt(self.spr, [0])
+        self.mask = FieldSelectableInt(self.spr, tuple(range(1,4)))
+        self.elwidth = FieldSelectableInt(self.spr, tuple(range(4,6)))
+        self.ewsrc = FieldSelectableInt(self.spr, tuple(range(6,8)))
+        self.subvl = FieldSelectableInt(self.spr, tuple(range(8,10)))
+        self.extra = FieldSelectableInt(self.spr, tuple(range(10,19)))
+        self.mode = FieldSelectableInt(self.spr, tuple(range(19,24)))
+
+
 class SPR(dict):
     def __init__(self, dec2, initial_sprs={}):
         self.sd = dec2
@@ -274,6 +289,7 @@ class ISACaller:
     # respect_pc - tracks the program counter.  requires initial_insns
     def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
                  initial_mem=None, initial_msr=0,
+                 initial_svstate=0,
                  initial_insns=None, respect_pc=False,
                  disassembly=None,
                  initial_pc=0,
@@ -314,6 +330,7 @@ class ISACaller:
         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
         self.pc = PC()
+        self.svstate = SVSTATE(initial_svstate)
         self.spr = SPR(decoder2, initial_sprs)
         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
 
@@ -336,7 +353,7 @@ class ISACaller:
         #self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))
 
         # "undefined", just set to variable-bit-width int (use exts "max")
-        self.undefined = SelectableInt(0, 256)  # TODO, not hard-code 256!
+        #self.undefined = SelectableInt(0, 256)  # TODO, not hard-code 256!
 
         self.namespace = {}
         self.namespace.update(self.spr)
@@ -348,7 +365,7 @@ class ISACaller:
                                'CIA': self.pc.CIA,
                                'CR': self.cr,
                                'MSR': self.msr,
-                               'undefined': self.undefined,
+                               'undefined': undefined,
                                'mode_is_64bit': True,
                                'SO': XER_bits['SO']
                                })