add a DIVS function as separate and discrete from floor_div

[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 7d73551ae9ff894a2bd2f15040a738307e6b07e5..ef6e46dd6d8bea6c18266cf72a0df5ceb4c1fdad 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -3,6 +3,10 @@
 this is part of a cycle-accurate POWER9 simulator.  its primary purpose is
 not speed, it is for both learning and educational purposes, as well as
 a method of verifying the HDL.
+
+related bugs:
+
+* https://bugs.libre-soc.org/show_bug.cgi?id=424
 """
 
 from functools import wraps
@@ -11,7 +15,7 @@ from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
                                         selectconcat)
 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
                                      insns, InternalOp)
-from soc.decoder.helpers import exts, trunc_div, trunc_rem
+from soc.decoder.helpers import exts
 from soc.consts import PI, MSR
 
 from collections import namedtuple
@@ -245,8 +249,10 @@ class ISACaller:
                        initial_mem=None, initial_msr=0,
                        initial_insns=None, respect_pc=False,
                        disassembly=None,
-                       initial_pc=0):
+                       initial_pc=0,
+                       bigendian=True):
 
+        self.bigendian = bigendian
         self.halted = False
         self.respect_pc = respect_pc
         if initial_sprs is None:
@@ -413,13 +419,13 @@ class ISACaller:
             inputs.append(SelectableInt(imm, 64))
         assert len(outputs) >= 1
         print ("handle_overflow", inputs, outputs, div_overflow)
-        if len(inputs) < 2 and div_overflow != 1:
+        if len(inputs) < 2 and div_overflow is None:
             return
 
         # div overflow is different: it's returned by the pseudo-code
         # because it's more complex than can be done by analysing the output
-        if div_overflow == 1:
-            ov, ov32 = 1, 1
+        if div_overflow is not None:
+            ov, ov32 = div_overflow, div_overflow
         # arithmetic overflow can be done by analysing the input and output
         elif len(inputs) >= 2:
             output = outputs[0]
@@ -444,11 +450,19 @@ class ISACaller:
 
     def handle_comparison(self, outputs):
         out = outputs[0]
+        print ("handle_comparison", out.bits, hex(out.value))
+        # TODO - XXX *processor* in 32-bit mode
+        # https://bugs.libre-soc.org/show_bug.cgi?id=424
+        #if is_32bit:
+        #    o32 = exts(out.value, 32)
+        #    print ("handle_comparison exts 32 bit", hex(o32))
         out = exts(out.value, out.bits)
+        print ("handle_comparison exts", hex(out))
         zero = SelectableInt(out == 0, 1)
         positive = SelectableInt(out > 0, 1)
         negative = SelectableInt(out < 0, 1)
         SO = self.spr['XER'][XER_bits['SO']]
+        print ("handle_comparison SO", SO)
         cr_field = selectconcat(negative, positive, zero, SO)
         self.crl[0].eq(cr_field)
 
@@ -471,7 +485,7 @@ class ISACaller:
         print ("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
 
         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
-        yield self.dec2.dec.bigendian.eq(0)  # little / big?
+        yield self.dec2.dec.bigendian.eq(self.bigendian)
 
     def execute_one(self):
         """execute one instruction
@@ -490,6 +504,7 @@ class ISACaller:
         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
         asmcode = yield self.dec2.dec.op.asmcode
+        print ("get assembly name asmcode", asmcode)
         asmop = insns.get(asmcode, None)
 
         # sigh reconstruct the assembly instruction name
@@ -524,6 +539,7 @@ class ISACaller:
         return asmop
 
     def call(self, name):
+        name = name.strip() # remove spaces if not already done so
         if self.halted:
             print ("halted - not executing", name)
             return
@@ -532,6 +548,13 @@ class ISACaller:
         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
         asmop = yield from self.get_assembly_name()
         print  ("call", name, asmop)
+
+        # check halted condition
+        if name == 'attn':
+            self.halted = True
+            return
+
+        # check illegal instruction
         illegal = False
         if name not in ['mtcrf', 'mtocrf']:
             illegal = name != asmop
@@ -543,10 +566,6 @@ class ISACaller:
             self.pc.update(self.namespace)
             return
 
-        if name == 'attn':
-            self.halted = True
-            return
-
         info = self.instrs[name]
         yield from self.prep_namespace(info.form, info.op_fields)