update test case for radix mmu

[soc.git] / src / soc / decoder / isa / test_caller.py

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 4ed0577c0fd22a52503c818f371d323e82b8ef7c..77b54c7c95b5a84e38ff3b0948fbcdb7d8ef9966 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -17,7 +17,7 @@ class Register:
         self.num = num
 
 def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
-                                     initial_cr=0):
+                                     initial_cr=0,mem=None):
     if initial_sprs is None:
         initial_sprs = {}
     m = Module()
@@ -34,6 +34,7 @@ def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
     simulator = ISA(pdecode2, initial_regs, initial_sprs, initial_cr,
                     initial_insns=gen, respect_pc=True,
                     initial_svstate=svstate,
+                    initial_mem=mem,
                     disassembly=insncode,
                     bigendian=0,
                     mmu=mmu)