Add test for prtyw pseudocode

[soc.git] / src / soc / decoder / isa / test_caller.py

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 6e3ccdd25bbdd7f326ab1150a24e933525b30647..10db874c344b29fef311b3d731c49fd0207f1f25 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -19,7 +19,7 @@ class Register:
 
 class DecoderTestCase(FHDLTestCase):
 
-    def run_tst(self, generator, initial_regs):
+    def run_tst(self, generator, initial_regs, initial_sprs={}):
         m = Module()
         comb = m.d.comb
         instruction = Signal(32)
@@ -27,7 +27,7 @@ class DecoderTestCase(FHDLTestCase):
         pdecode = create_pdecode()
 
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
-        simulator = ISA(pdecode2, initial_regs)
+        simulator = ISA(pdecode2, initial_regs, initial_sprs)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)
         gen = generator.generate_instructions()
@@ -128,6 +128,46 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(1), SelectableInt(0x1234, 64))
             self.assertEqual(sim.gpr(2), SelectableInt(0, 64))
 
+    def test_branch_cond(self):
+        for i in [0, 10]:
+            lst = [f"addi 1, 0, {i}",  # set r1 to i
+                "cmpi cr0, 1, 1, 10",  # compare r1 with 10 and store to cr0
+                "bc 12, 2, 0x8",       # beq 0x8 -
+                                       # branch if r1 equals 10 to the nop below
+                "addi 2, 0, 0x1234",   # if r1 == 10 this shouldn't execute
+                "or 0, 0, 0"]          # branch target
+            with Program(lst) as program:
+                sim = self.run_tst_program(program)
+                if i == 10:
+                    self.assertEqual(sim.gpr(2), SelectableInt(0, 64))
+                else:
+                    self.assertEqual(sim.gpr(2), SelectableInt(0x1234, 64))
+
+    def test_branch_loop(self):
+        lst = ["addi 1, 0, 0",
+               "addi 1, 0, 0",
+               "addi 1, 1, 1",
+               "add  2, 2, 1",
+               "cmpi cr0, 1, 1, 10",
+               "bc 12, 0, -0xc"]
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+            # Verified with qemu
+            self.assertEqual(sim.gpr(2), SelectableInt(0x37, 64))
+
+    def test_branch_loop_ctr(self):
+        lst = ["addi 1, 0, 0",
+               "addi 2, 0, 7",
+               "mtspr 9, 2",    # set ctr to 7
+               "addi 1, 1, 5",
+               "bc 16, 0, -0x4"]  # bdnz to the addi above
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+            # Verified with qemu
+            self.assertEqual(sim.gpr(1), SelectableInt(0x23, 64))
+
+
+
     def test_add_compare(self):
         lst = ["addis 1, 0, 0xffff",
                "addis 2, 0, 0xffff",
@@ -141,11 +181,64 @@ class DecoderTestCase(FHDLTestCase):
     def test_cmp(self):
         lst = ["addis 1, 0, 0xffff",
                "addis 2, 0, 0xffff",
-               "cmp cr0, 0, 1, 2",
+               "cmp cr2, 0, 1, 2",
                "mfcr 3"]
         with Program(lst) as program:
             sim = self.run_tst_program(program)
-            self.assertEqual(sim.gpr(3), SelectableInt(0x20000000, 64))
+            self.assertEqual(sim.gpr(3), SelectableInt(0x200000, 64))
+
+    def test_slw(self):
+        lst = ["slw 1, 3, 2"]
+        initial_regs = [0] * 32
+        initial_regs[3] = 0xdeadbeefcafebabe
+        initial_regs[2] = 5
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+            self.assertEqual(sim.gpr(1), SelectableInt(0x5fd757c0, 64))
+
+    def test_srw(self):
+        lst = ["srw 1, 3, 2"]
+        initial_regs = [0] * 32
+        initial_regs[3] = 0xdeadbeefcafebabe
+        initial_regs[2] = 5
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+            self.assertEqual(sim.gpr(1), SelectableInt(0x657f5d5, 64))
+
+    def test_rlwinm(self):
+        lst = ["rlwinm 3, 1, 5, 20, 6"]
+        initial_regs = [0] * 32
+        initial_regs[1] = -1
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+            self.assertEqual(sim.gpr(3), SelectableInt(0xfffffffffe000fff, 64))
+
+    def test_rlwimi(self):
+        lst = ["rlwimi 3, 1, 5, 20, 6"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xffffffffdeadbeef
+        initial_regs[3] = 0x12345678
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+            self.assertEqual(sim.gpr(3), SelectableInt(0xd5b7ddfbd4345dfb, 64))
+
+    def test_rldic(self):
+        lst = ["rldic 3, 1, 5, 20"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xdeadbeefcafec0de
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+            self.assertEqual(sim.gpr(3), SelectableInt(0xdf95fd81bc0, 64))
+
+    def test_prty(self):
+        lst = ["prtyw 2, 1"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xdeadbeeecaffc0de
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+            self.assertEqual(sim.gpr(2), SelectableInt(0x100000001, 64))
+
+        
 
     def test_mtcrf(self):
         for i in range(4):