Add test for prtyw pseudocode

[soc.git] / src / soc / decoder / isa / test_caller.py

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index f1224f4869a82c23761fc39787502e8a22741269..10db874c344b29fef311b3d731c49fd0207f1f25 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -181,11 +181,11 @@ class DecoderTestCase(FHDLTestCase):
     def test_cmp(self):
         lst = ["addis 1, 0, 0xffff",
                "addis 2, 0, 0xffff",
-               "cmp cr0, 0, 1, 2",
+               "cmp cr2, 0, 1, 2",
                "mfcr 3"]
         with Program(lst) as program:
             sim = self.run_tst_program(program)
-            self.assertEqual(sim.gpr(3), SelectableInt(0x20000000, 64))
+            self.assertEqual(sim.gpr(3), SelectableInt(0x200000, 64))
 
     def test_slw(self):
         lst = ["slw 1, 3, 2"]
@@ -211,16 +211,34 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[1] = -1
         with Program(lst) as program:
             sim = self.run_tst_program(program, initial_regs)
-            self.assertEqual(sim.gpr(3), SelectableInt(0xfe000fff, 64))
+            self.assertEqual(sim.gpr(3), SelectableInt(0xfffffffffe000fff, 64))
 
     def test_rlwimi(self):
         lst = ["rlwimi 3, 1, 5, 20, 6"]
         initial_regs = [0] * 32
-        initial_regs[1] = 0xdeadbeef
+        initial_regs[1] = 0xffffffffdeadbeef
         initial_regs[3] = 0x12345678
         with Program(lst) as program:
             sim = self.run_tst_program(program, initial_regs)
-            self.assertEqual(sim.gpr(3), SelectableInt(0xd4345dfb, 64))
+            self.assertEqual(sim.gpr(3), SelectableInt(0xd5b7ddfbd4345dfb, 64))
+
+    def test_rldic(self):
+        lst = ["rldic 3, 1, 5, 20"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xdeadbeefcafec0de
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+            self.assertEqual(sim.gpr(3), SelectableInt(0xdf95fd81bc0, 64))
+
+    def test_prty(self):
+        lst = ["prtyw 2, 1"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xdeadbeeecaffc0de
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+            self.assertEqual(sim.gpr(2), SelectableInt(0x100000001, 64))
+
+        
 
     def test_mtcrf(self):
         for i in range(4):