Add tests for conditional branches

[soc.git] / src / soc / decoder / isa / test_caller.py

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index f072393d2f73594bb69eee16e91b1c279a2f98ea..15a8997ed2e435580f4c7e7e3aa1108c50e74f0f 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -25,15 +25,19 @@ class DecoderTestCase(FHDLTestCase):
         instruction = Signal(32)
 
         pdecode = create_pdecode()
-        simulator = ISA(pdecode, initial_regs)
 
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+        simulator = ISA(pdecode2, initial_regs)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)
         gen = generator.generate_instructions()
 
         def process():
-            for ins, code in zip(gen, generator.assembly.splitlines()):
+            instructions = list(zip(gen, generator.assembly.splitlines()))
+
+            index = simulator.pc.CIA.value//4
+            while index < len(instructions):
+                ins, code = instructions[index]
 
                 print("0x{:X}".format(ins & 0xffffffff))
                 print(code)
@@ -44,6 +48,7 @@ class DecoderTestCase(FHDLTestCase):
                 yield Delay(1e-6)
                 opname = code.split(' ')[0]
                 yield from simulator.call(opname)
+                index = simulator.pc.CIA.value//4
 
         sim.add_process(process)
         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
@@ -89,20 +94,104 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(2), SelectableInt(0x10008, 64))
             self.assertEqual(sim.gpr(3), SelectableInt(0x1000c, 64))
 
+    def test_branch(self):
+        lst = ["ba 0xc",             # branch to line 4
+               "addi 1, 0, 0x1234",  # Should never execute
+               "ba 0x1000",          # exit the program
+               "addi 2, 0, 0x1234",  # line 4
+               "ba 0x8"]             # branch to line 3
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+            self.assertEqual(sim.pc.CIA, SelectableInt(0x1000, 64))
+            self.assertEqual(sim.gpr(1), SelectableInt(0x0, 64))
+            self.assertEqual(sim.gpr(2), SelectableInt(0x1234, 64))
+
+    def test_branch_link(self):
+        lst = ["bl 0xc",
+               "addi 2, 1, 0x1234",
+               "ba 0x1000",
+               "addi 1, 0, 0x1234",
+               "bclr 20, 0, 0"]
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+            self.assertEqual(sim.spr['LR'], SelectableInt(0x4, 64))
+
+    def test_branch_ctr(self):
+        lst = ["addi 1, 0, 0x10",    # target of jump
+               "mtspr 9, 1",         # mtctr 1
+               "bcctr 20, 0, 0",     # bctr
+               "addi 2, 0, 0x1",     # should never execute
+               "addi 1, 0, 0x1234"]  # target of ctr
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+            self.assertEqual(sim.spr['CTR'], SelectableInt(0x10, 64))
+            self.assertEqual(sim.gpr(1), SelectableInt(0x1234, 64))
+            self.assertEqual(sim.gpr(2), SelectableInt(0, 64))
+
+    def test_branch_cond(self):
+        for i in [0, 10]:
+            lst = [f"addi 1, 0, {i}",  # set r1 to i
+                "cmpi cr0, 1, 1, 10",  # compare r1 with 10 and store to cr0
+                "bc 12, 2, 0x8",       # beq 0x8 -
+                                       # branch if r1 equals 10 to the nop below
+                "addi 2, 0, 0x1234",   # if r1 == 10 this shouldn't execute
+                "or 0, 0, 0"]          # branch target
+            with Program(lst) as program:
+                sim = self.run_tst_program(program)
+                if i == 10:
+                    self.assertEqual(sim.gpr(2), SelectableInt(0, 64))
+                else:
+                    self.assertEqual(sim.gpr(2), SelectableInt(0x1234, 64))
+
+    def test_branch_loop(self):
+        lst = ["addi 1, 0, 0",
+               "addi 1, 0, 0",
+               "addi 1, 1, 1",
+               "add  2, 2, 1",
+               "cmpi cr0, 1, 1, 10",
+               "bc 12, 0, -0xc"]
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+            # Verified with qemu
+            self.assertEqual(sim.gpr(2), SelectableInt(0x37, 64))
+                    
+
+    def test_add_compare(self):
+        lst = ["addis 1, 0, 0xffff",
+               "addis 2, 0, 0xffff",
+               "add. 1, 1, 2",
+               "mfcr 3"]
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+            # Verified with QEMU
+            self.assertEqual(sim.gpr(3), SelectableInt(0x80000000, 64))
+
+    def test_cmp(self):
+        lst = ["addis 1, 0, 0xffff",
+               "addis 2, 0, 0xffff",
+               "cmp cr0, 0, 1, 2",
+               "mfcr 3"]
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+            self.assertEqual(sim.gpr(3), SelectableInt(0x20000000, 64))
+
     def test_mtcrf(self):
         for i in range(4):
-            # 0x7654 gives expected (3+4) (2+4) (1+4) (0+4) for i=3,2,1,0
-            lst = ["addi %d, 0, 0x7654" % (i+1),
-                   "mtcrf %d, %d" % (1<<i, i+1),
-                                   ]
+            # 0x76540000 gives expected (3+4) (2+4) (1+4) (0+4) for
+            #     i=0, 1, 2, 3
+            # The positions of the CR fields have been verified using
+            # QEMU and 'cmp crx, a, b' instructions
+            lst = ["addis 1, 0, 0x7654",
+                   "mtcrf %d, 1" % (1 << (7-i)),
+                   ]
             with Program(lst) as program:
                 sim = self.run_tst_program(program)
-            print ("cr", sim.cr)
-            expected = (i+4)
+            print("cr", sim.cr)
+            expected = (7-i)
             # check CR itself
-            self.assertEqual(sim.cr, SelectableInt(expected<<(i*4), 32))
+            self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 32))
             # check CR[0]/1/2/3 as well
-            print ("cr%d", sim.crl[i])
+            print("cr%d", sim.crl[i])
             self.assertTrue(SelectableInt(expected, 4) == sim.crl[i])
 
     def run_tst_program(self, prog, initial_regs=[0] * 32):