Re-enable test_mtcrf

[soc.git] / src / soc / decoder / isa / test_caller.py

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 0a26c8169883112d431b55828535038066e56633..21364340e5395a27c2951a34d5ae63d8bb8964e8 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -33,7 +33,11 @@ class DecoderTestCase(FHDLTestCase):
         gen = generator.generate_instructions()
 
         def process():
-            for ins, code in zip(gen, generator.assembly.splitlines()):
+            instructions = list(zip(gen, generator.assembly.splitlines()))
+
+            index = simulator.pc.CIA.value//4
+            while index < len(instructions):
+                ins, code = instructions[index]
 
                 print("0x{:X}".format(ins & 0xffffffff))
                 print(code)
@@ -44,6 +48,7 @@ class DecoderTestCase(FHDLTestCase):
                 yield Delay(1e-6)
                 opname = code.split(' ')[0]
                 yield from simulator.call(opname)
+                index = simulator.pc.CIA.value//4
 
         sim.add_process(process)
         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
@@ -89,6 +94,59 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(2), SelectableInt(0x10008, 64))
             self.assertEqual(sim.gpr(3), SelectableInt(0x1000c, 64))
 
+    def test_branch(self):
+        lst = ["ba 0xc",             # branch to line 4
+               "addi 1, 0, 0x1234",  # Should never execute
+               "ba 0x1000",          # exit the program
+               "addi 2, 0, 0x1234",  # line 4
+               "ba 0x8"]             # branch to line 3
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+            self.assertEqual(sim.pc.CIA, SelectableInt(0x1000, 64))
+            self.assertEqual(sim.gpr(1), SelectableInt(0x0, 64))
+            self.assertEqual(sim.gpr(2), SelectableInt(0x1234, 64))
+
+    def test_branch_link(self):
+        lst = ["bl 0xc",
+               "addi 2, 1, 0x1234",
+               "ba 0x1000",
+               "addi 1, 0, 0x1234",
+               "bclr 20, 0, 0"]
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+            self.assertEqual(sim.spr['LR'], SelectableInt(0x4, 64))
+
+    def test_branch_ctr(self):
+        lst = ["addi 1, 0, 0x10",    # target of jump
+               "mtspr 9, 1",         # mtctr 1
+               "bcctr 20, 0, 0",     # bctr
+               "addi 2, 0, 0x1",     # should never execute
+               "addi 1, 0, 0x1234"]  # target of ctr
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+            self.assertEqual(sim.spr['CTR'], SelectableInt(0x10, 64))
+            self.assertEqual(sim.gpr(1), SelectableInt(0x1234, 64))
+            self.assertEqual(sim.gpr(2), SelectableInt(0, 64))
+
+
+
+
+    def test_mtcrf(self):
+        for i in range(4):
+            # 0x7654 gives expected (3+4) (2+4) (1+4) (0+4) for i=3,2,1,0
+            lst = ["addi %d, 0, 0x7654" % (i+1),
+                   "mtcrf %d, %d" % (1 << i, i+1),
+                   ]
+            with Program(lst) as program:
+                sim = self.run_tst_program(program)
+            print("cr", sim.cr)
+            expected = (i+4)
+            # check CR itself
+            self.assertEqual(sim.cr, SelectableInt(expected << (i*4), 32))
+            # check CR[0]/1/2/3 as well
+            print("cr%d", sim.crl[i])
+            self.assertTrue(SelectableInt(expected, 4) == sim.crl[i])
+
     def run_tst_program(self, prog, initial_regs=[0] * 32):
         simulator = self.run_tst(prog, initial_regs)
         simulator.gpr.dump()