from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
from soc.simulator.program import Program
-from soc.simulator.qemu import run_program
from soc.decoder.isa.caller import ISACaller, inject
-from soc.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,)
from soc.decoder.selectable_int import SelectableInt
-from soc.decoder.selectable_int import selectconcat as concat
from soc.decoder.orderedset import OrderedSet
-
-class fixedarith(ISACaller):
-
- @inject()
- def op_addi(self, RA):
- if RA == 0:
- RT = SI
- else:
- RT = RA + SI
- return (RT,)
- @inject()
- def op_add(self, RA, RB):
- RT = RA + RB
- return (RT,)
-
- instrs = {}
- instrs['addi'] = (op_addi, OrderedSet(['RA']),
- OrderedSet(), OrderedSet(['RT']))
- instrs['add'] = (op_add, OrderedSet(['RA', 'RB']),
- OrderedSet(), OrderedSet(['RT']))
-
+from soc.decoder.isa.all import ISA
class Register:
instruction = Signal(32)
pdecode = create_pdecode()
- simulator = fixedarith(pdecode, initial_regs)
+ simulator = ISA(pdecode, initial_regs)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
gen = generator.generate_instructions()
def process():
- for ins, code in zip(gen, generator.assembly.splitlines()):
+ instructions = list(zip(gen, generator.assembly.splitlines()))
+
+ index = simulator.pc.CIA.value//4
+ while index < len(instructions):
+ ins, code = instructions[index]
print("0x{:X}".format(ins & 0xffffffff))
print(code)
yield Delay(1e-6)
opname = code.split(' ')[0]
yield from simulator.call(opname)
+ index = simulator.pc.CIA.value//4
sim.add_process(process)
with sim.write_vcd("simulator.vcd", "simulator.gtkw",
initial_regs[3] = 0x1234
initial_regs[2] = 0x4321
with Program(lst) as program:
- sim = self.run_test_program(program, initial_regs)
+ sim = self.run_tst_program(program, initial_regs)
+ self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
+
+ def test_addi(self):
+ lst = ["addi 3, 0, 0x1234",
+ "addi 2, 0, 0x4321",
+ "add 1, 3, 2"]
+ with Program(lst) as program:
+ sim = self.run_tst_program(program)
+ print(sim.gpr(1))
self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
- def run_test_program(self, prog, initial_regs):
+ def test_load_store(self):
+ lst = ["addi 1, 0, 0x0010",
+ "addi 2, 0, 0x1234",
+ "stw 2, 0(1)",
+ "lwz 3, 0(1)"]
+ with Program(lst) as program:
+ sim = self.run_tst_program(program)
+ print(sim.gpr(1))
+ self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
+
+ def test_addpcis(self):
+ lst = ["addpcis 1, 0x1",
+ "addpcis 2, 0x1",
+ "addpcis 3, 0x1"]
+ with Program(lst) as program:
+ sim = self.run_tst_program(program)
+ self.assertEqual(sim.gpr(1), SelectableInt(0x10004, 64))
+ self.assertEqual(sim.gpr(2), SelectableInt(0x10008, 64))
+ self.assertEqual(sim.gpr(3), SelectableInt(0x1000c, 64))
+
+ def test_branch(self):
+ lst = ["ba 0xc", # branch to line 4
+ "addi 1, 0, 0x1234", # Should never execute
+ "ba 0x1000", # exit the program
+ "addi 2, 0, 0x1234", # line 4
+ "ba 0x8"] # branch to line 3
+ with Program(lst) as program:
+ sim = self.run_tst_program(program)
+ self.assertEqual(sim.pc.CIA, SelectableInt(0x1000, 64))
+ self.assertEqual(sim.gpr(1), SelectableInt(0x0, 64))
+ self.assertEqual(sim.gpr(2), SelectableInt(0x1234, 64))
+
+ def test_branch_link(self):
+ lst = ["bl 0xc",
+ "addi 2, 1, 0x1234",
+ "ba 0x1000",
+ "addi 1, 0, 0x1234",
+ "bclr 20, 0, 0"]
+ with Program(lst) as program:
+ sim = self.run_tst_program(program)
+ self.assertEqual(sim.spr['LR'], SelectableInt(0x4, 64))
+
+ def test_branch_ctr(self):
+ lst = ["addi 1, 0, 0x10", # target of jump
+ "mtspr 9, 1", # mtctr 1
+ "bcctr 20, 0, 0", # bctr
+ "addi 2, 0, 0x1", # should never execute
+ "addi 1, 0, 0x1234"] # target of ctr
+ with Program(lst) as program:
+ sim = self.run_tst_program(program)
+ self.assertEqual(sim.spr['CTR'], SelectableInt(0x10, 64))
+ self.assertEqual(sim.gpr(1), SelectableInt(0x1234, 64))
+ self.assertEqual(sim.gpr(2), SelectableInt(0, 64))
+
+
+
+
+ def test_mtcrf(self):
+ for i in range(4):
+ # 0x7654 gives expected (3+4) (2+4) (1+4) (0+4) for i=3,2,1,0
+ lst = ["addi %d, 0, 0x7654" % (i+1),
+ "mtcrf %d, %d" % (1 << i, i+1),
+ ]
+ with Program(lst) as program:
+ sim = self.run_tst_program(program)
+ print("cr", sim.cr)
+ expected = (i+4)
+ # check CR itself
+ self.assertEqual(sim.cr, SelectableInt(expected << (i*4), 32))
+ # check CR[0]/1/2/3 as well
+ print("cr%d", sim.crl[i])
+ self.assertTrue(SelectableInt(expected, 4) == sim.crl[i])
+
+ def run_tst_program(self, prog, initial_regs=[0] * 32):
simulator = self.run_tst(prog, initial_regs)
simulator.gpr.dump()
return simulator
+
if __name__ == "__main__":
unittest.main()
projects / soc.git / blobdiff