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add srcstep and correct PC-advancing during Sub-PC looping in ISACaller
[soc.git]
/
src
/
soc
/
decoder
/
isa
/
test_caller.py
diff --git
a/src/soc/decoder/isa/test_caller.py
b/src/soc/decoder/isa/test_caller.py
index 8f190ca0625bf3b5e2bb06d1d58a83b43aed5ca6..691d9a71357b2fd2211e946fa0f4d731f2b70775 100644
(file)
--- a/
src/soc/decoder/isa/test_caller.py
+++ b/
src/soc/decoder/isa/test_caller.py
@@
-53,7
+53,7
@@
def run_tst(generator, initial_regs, initial_sprs=None, svstate=0):
yield Settle()
ins, code = instructions[index]
yield Settle()
ins, code = instructions[index]
- print("0x{:X}".format(ins & 0xffffffff))
+ print("
0x{:X}".format(ins & 0xffffffff))
opname = code.split(' ')[0]
print(code, opname)
opname = code.split(' ')[0]
print(code, opname)