+def run_tst(generator, initial_regs, initial_sprs=None, svstate=0):
+ if initial_sprs is None:
+ initial_sprs = {}
+ m = Module()
+ comb = m.d.comb
+ instruction = Signal(32)
+
+ pdecode = create_pdecode()
+
+ gen = list(generator.generate_instructions())
+ insncode = generator.assembly.splitlines()
+ instructions = list(zip(gen, insncode))
+
+ m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
+ simulator = ISA(pdecode2, initial_regs, initial_sprs, 0,
+ initial_insns=gen, respect_pc=True,
+ initial_svstate=svstate,
+ disassembly=insncode,
+ bigendian=0)
+ comb += pdecode2.dec.raw_opcode_in.eq(instruction)
+ sim = Simulator(m)
+
+
+ def process():
+
+ yield pdecode2.dec.bigendian.eq(0) # little / big?
+ pc = simulator.pc.CIA.value
+ index = pc//4
+ while index < len(instructions):
+ print("instr pc", pc)
+ try:
+ yield from simulator.setup_one()
+ except KeyError: # indicates instruction not in imem: stop
+ break
+ yield Settle()
+
+ ins, code = instructions[index]
+ print(" 0x{:X}".format(ins & 0xffffffff))
+ opname = code.split(' ')[0]
+ print(code, opname)
+
+ # ask the decoder to decode this binary data (endian'd)
+ yield from simulator.execute_one()
+ pc = simulator.pc.CIA.value
+ index = pc//4