add srcstep and correct PC-advancing during Sub-PC looping in ISACaller

[soc.git] / src / soc / decoder / isa / test_caller.py

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index a43f4a28405f19141cfea0aad40dc7bc86d8c966..691d9a71357b2fd2211e946fa0f4d731f2b70775 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -16,7 +16,9 @@ class Register:
     def __init__(self, num):
         self.num = num
 
-def run_tst(generator, initial_regs, initial_sprs={}):
+def run_tst(generator, initial_regs, initial_sprs=None, svstate=0):
+    if initial_sprs is None:
+        initial_sprs = {}
     m = Module()
     comb = m.d.comb
     instruction = Signal(32)
@@ -30,6 +32,7 @@ def run_tst(generator, initial_regs, initial_sprs={}):
     m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
     simulator = ISA(pdecode2, initial_regs, initial_sprs, 0,
                     initial_insns=gen, respect_pc=True,
+                    initial_svstate=svstate,
                     disassembly=insncode,
                     bigendian=0)
     comb += pdecode2.dec.raw_opcode_in.eq(instruction)
@@ -50,7 +53,7 @@ def run_tst(generator, initial_regs, initial_sprs={}):
             yield Settle()
 
             ins, code = instructions[index]
-            print("0x{:X}".format(ins & 0xffffffff))
+            print("    0x{:X}".format(ins & 0xffffffff))
             opname = code.split(' ')[0]
             print(code, opname)