starting to add SVP64 register EXTRA-read and isvec to ISACaller

[soc.git] / src / soc / decoder / isa / test_caller.py

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 684b38aae51f022dcb8e0cae615d9fee318fc332..a43f4a28405f19141cfea0aad40dc7bc86d8c966 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -38,6 +38,7 @@ def run_tst(generator, initial_regs, initial_sprs={}):
 
     def process():
 
+        yield pdecode2.dec.bigendian.eq(0)  # little / big?
         pc = simulator.pc.CIA.value
         index = pc//4
         while index < len(instructions):
@@ -50,14 +51,11 @@ def run_tst(generator, initial_regs, initial_sprs={}):
 
             ins, code = instructions[index]
             print("0x{:X}".format(ins & 0xffffffff))
-            print(code)
+            opname = code.split(' ')[0]
+            print(code, opname)
 
             # ask the decoder to decode this binary data (endian'd)
-            yield pdecode2.dec.bigendian.eq(0)  # little / big?
-            yield instruction.eq(ins)          # raw binary instr.
-            yield Delay(1e-6)
-            opname = code.split(' ')[0]
-            yield from simulator.call(opname)
+            yield from simulator.execute_one()
             pc = simulator.pc.CIA.value
             index = pc//4