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[soc.git] / src / soc / decoder / isa / test_caller_radix.py

diff --git a/src/soc/decoder/isa/test_caller_radix.py b/src/soc/decoder/isa/test_caller_radix.py
index 3c1636e221b0af5693a35aa519d6695d1fba7bdc..338a894b7cf427552b9b0858a32b136f21bfcece 100644 (file)
--- a/src/soc/decoder/isa/test_caller_radix.py
+++ b/src/soc/decoder/isa/test_caller_radix.py
@@ -57,7 +57,7 @@ class DecoderTestCase(FHDLTestCase):
                'PRTBL': SelectableInt(prtbl, 64)
         }
 
-        simulator = run_tst(prog, initial_regs,mmu=True,mem=testmem,
+        simulator = run_tst(prog, initial_regs, mmu=True, mem=testmem,
                     initial_sprs=spr)
         simulator.gpr.dump()
         return simulator