add in SVSTATE to ISACaller, not used, just passed in

[soc.git] / src / soc / decoder / isa / test_caller_svp64.py

diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py
index c9d1391a424b8e2e59e2ca5d170a068d4e46bf6c..34af4831a3d2e2cd10f44ac5c478a0dd6de85881 100644 (file)
--- a/src/soc/decoder/isa/test_caller_svp64.py
+++ b/src/soc/decoder/isa/test_caller_svp64.py
@@ -6,7 +6,7 @@ from soc.decoder.isa.caller import ISACaller
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.simulator.program import Program
-from soc.decoder.isa.caller import ISACaller, inject
+from soc.decoder.isa.caller import ISACaller, SVP64State
 from soc.decoder.selectable_int import SelectableInt
 from soc.decoder.orderedset import OrderedSet
 from soc.decoder.isa.all import ISA
@@ -25,12 +25,17 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs = [0] * 32
         initial_regs[3] = 0x1234
         initial_regs[2] = 0x4321
+        svstate = SVP64State()
+        svstate.vl[0:-1] = 2 # VL
+        svstate.maxvl[0:-1] = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.spr.asint()))
         with Program(lst, bigendian=False) as program:
-            sim = self.run_tst_program(program, initial_regs)
+            sim = self.run_tst_program(program, initial_regs, svstate)
             self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
 
-    def run_tst_program(self, prog, initial_regs=[0] * 32):
-        simulator = run_tst(prog, initial_regs)
+    def run_tst_program(self, prog, initial_regs=[0] * 32,
+                              svstate=None):
+        simulator = run_tst(prog, initial_regs, svstate=svstate)
         simulator.gpr.dump()
         return simulator