use SPR constants

[soc.git] / src / soc / decoder / power_decoder2.py

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index b581922b01095f68d19906fcae7dc4969737e0a5..0f4c16a2190e98a14e93c744c53e1c3c53066e6d 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -23,7 +23,8 @@ from soc.decoder.power_enums import (MicrOp, CryIn, Function,
                                      CRInSel, CROutSel,
                                      LdstLen, In1Sel, In2Sel, In3Sel,
                                      OutSel, SPR, RC, LDSTMode)
-from soc.decoder.decode2execute1 import Decode2ToExecute1Type, Data
+from soc.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
+                                         Decode2ToOperand)
 from soc.consts import MSR
 
 from soc.regfile.regfiles import FastRegs
@@ -622,14 +623,22 @@ record_names = {'insn_type': 'internal_op',
 
 class PowerDecodeSubset(Elaboratable):
     """PowerDecodeSubset: dynamic subset decoder
+
+    only fields actually requested are copied over. hence, "subset" (duh).
     """
     def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None):
 
         self.final = final
         self.opkls = opkls
         self.fn_name = fn_name
-        self.e = Decode2ToExecute1Type(name=self.fn_name, opkls=self.opkls)
-        col_subset = self.get_col_subset(self.e.do)
+        if opkls is None:
+            opkls = Decode2ToOperand
+        self.do = opkls(fn_name)
+        col_subset = self.get_col_subset(self.do)
+
+        # only needed for "main" PowerDecode2
+        if not self.final:
+            self.e = Decode2ToExecute1Type(name=self.fn_name, do=self.do)
 
         # create decoder if one not already given
         if dec is None:
@@ -658,14 +667,14 @@ class PowerDecodeSubset(Elaboratable):
 
     def needs_field(self, field, op_field):
         if self.final:
-            do = self.e.do
+            do = self.do
         else:
             do = self.e_tmp.do
         return hasattr(do, field) and self.op_get(op_field) is not None
 
     def do_copy(self, field, val, final=False):
         if final or self.final:
-            do = self.e.do
+            do = self.do
         else:
             do = self.e_tmp.do
         if hasattr(do, field) and val is not None:
@@ -679,20 +688,17 @@ class PowerDecodeSubset(Elaboratable):
         m = Module()
         comb = m.d.comb
         state = self.state
-        e_out, op, do_out = self.e, self.dec.op, self.e.do
+        op, do = self.dec.op, self.do
         msr, cia = state.msr, state.pc
 
         # fill in for a normal instruction (not an exception)
         # copy over if non-exception, non-privileged etc. is detected
-        if self.final:
-            e = self.e
-        else:
+        if not self.final:
             if self.fn_name is None:
                 name = "tmp"
             else:
                 name = self.fn_name + "tmp"
-            self.e_tmp = e = Decode2ToExecute1Type(name=name, opkls=self.opkls)
-        do = e.do
+            self.e_tmp = Decode2ToExecute1Type(name=name, opkls=self.opkls)
 
         # set up submodule decoders
         m.submodules.dec = self.dec
@@ -718,10 +724,24 @@ class PowerDecodeSubset(Elaboratable):
         comb += self.do_copy("msr", msr)
         comb += self.do_copy("cia", cia)
 
-        # set up instruction, pick fn unit
+        # set up instruction type
         # no op: defaults to OP_ILLEGAL
         comb += self.do_copy("insn_type", self.op_get("internal_op"))
-        comb += self.do_copy("fn_unit", self.op_get("function_unit"))
+
+        # function unit for decoded instruction: requires minor redirect
+        # for SPR set/get
+        fn = self.op_get("function_unit")
+        spr = Signal(10, reset_less=True)
+        comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
+
+        # for first test only forward SPRs 18 and 19 to MMU, when
+        # operation is MTSPR or MFSPR.  TODO: add other MMU SPRs
+        with m.If(((self.dec.op.internal_op == MicrOp.OP_MTSPR) |
+                   (self.dec.op.internal_op == MicrOp.OP_MFSPR)) &
+                  ((spr == SPR.DSISR) | (spr == SPR.DAR))):
+            comb += self.do_copy("fn_unit", Function.MMU)
+        with m.Else():
+            comb += self.do_copy("fn_unit",fn)
 
         # immediates
         if self.needs_field("zero_a", "in1_sel"):
@@ -911,22 +931,18 @@ class PowerDecode2(PowerDecodeSubset):
         # after a failed LD/ST.
         with m.If(exc.happened):
             with m.If(exc.alignment):
-                self.trap(m, TT.MEMEXC, 0x600)
+                self.trap(m, TT.PRIV, 0x600)
             with m.Elif(exc.instr_fault):
                 with m.If(exc.segment_fault):
-                    self.trap(m, TT.MEMEXC, 0x480)
+                    self.trap(m, TT.PRIV, 0x480)
                 with m.Else():
-                    # TODO
-                    #srr1(63 - 33) <= exc.invalid;
-                    #srr1(63 - 35) <= exc.perm_error; -- noexec fault
-                    #srr1(63 - 44) <= exc.badtree;
-                    #srr1(63 - 45) <= exc.rc_error;
+                    # pass exception info to trap to create SRR1
                     self.trap(m, TT.MEMEXC, 0x400, exc)
             with m.Else():
                 with m.If(exc.segment_fault):
-                    self.trap(m, TT.MEMEXC, 0x380)
+                    self.trap(m, TT.PRIV, 0x380)
                 with m.Else():
-                    self.trap(m, TT.MEMEXC, 0x300)
+                    self.trap(m, TT.PRIV, 0x300)
 
         # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
         with m.Elif(dec_irq_ok):