from nmutil.iocontrol import RecordObject
from nmutil.extend import exts
+from soc.experiment.mem_types import LDSTException
+
from soc.decoder.power_regspec_map import regspec_decode_read
from soc.decoder.power_regspec_map import regspec_decode_write
from soc.decoder.power_decoder import create_pdecode
CRInSel, CROutSel,
LdstLen, In1Sel, In2Sel, In3Sel,
OutSel, SPR, RC, LDSTMode)
-from soc.decoder.decode2execute1 import Decode2ToExecute1Type, Data
+from soc.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
+ Decode2ToOperand)
from soc.consts import MSR
from soc.regfile.regfiles import FastRegs
m = Module()
comb = m.d.comb
- # update mode LD/ST uses read-reg A also as an output
- with m.If(self.dec.op.upd == LDSTMode.update):
- comb += self.reg_out.eq(self.dec.RA)
- comb += self.reg_out.ok.eq(1)
+ if hasattr(self.dec.op, "upd"):
+ # update mode LD/ST uses read-reg A also as an output
+ with m.If(self.dec.op.upd == LDSTMode.update):
+ comb += self.reg_out.eq(self.dec.RA)
+ comb += self.reg_out.ok.eq(1)
# B, BC or BCREG: potential implicit register (LR) output
# these give bl, bcl, bclrl, etc.
'ldst_mode': 'upd',
}
+
class PowerDecodeSubset(Elaboratable):
"""PowerDecodeSubset: dynamic subset decoder
-
"""
-
- def __init__(self, dec, opkls=None, fn_name=None,
- final=False, state=None):
+ def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None):
self.final = final
self.opkls = opkls
self.fn_name = fn_name
- self.e = Decode2ToExecute1Type(name=self.fn_name, opkls=self.opkls)
- col_subset = self.get_col_subset(self.e.do)
+ if opkls is None:
+ opkls = Decode2ToOperand
+ self.do = opkls(fn_name)
+ col_subset = self.get_col_subset(self.do)
+
+ # only needed for "main" PowerDecode2
+ if not self.final:
+ self.e = Decode2ToExecute1Type(name=self.fn_name, do=self.do)
+ # create decoder if one not already given
if dec is None:
dec = create_pdecode(name=fn_name, col_subset=col_subset,
row_subset=self.rowsubsetfn)
def needs_field(self, field, op_field):
if self.final:
- do = self.e.do
+ do = self.do
else:
do = self.e_tmp.do
return hasattr(do, field) and self.op_get(op_field) is not None
def do_copy(self, field, val, final=False):
if final or self.final:
- do = self.e.do
+ do = self.do
else:
do = self.e_tmp.do
if hasattr(do, field) and val is not None:
m = Module()
comb = m.d.comb
state = self.state
- e_out, op, do_out = self.e, self.dec.op, self.e.do
+ op, do = self.dec.op, self.do
msr, cia = state.msr, state.pc
# fill in for a normal instruction (not an exception)
# copy over if non-exception, non-privileged etc. is detected
- if self.final:
- e = self.e
- else:
+ if not self.final:
if self.fn_name is None:
name = "tmp"
else:
name = self.fn_name + "tmp"
- self.e_tmp = e = Decode2ToExecute1Type(name=name, opkls=self.opkls)
- do = e.do
+ self.e_tmp = Decode2ToExecute1Type(name=name, opkls=self.opkls)
# set up submodule decoders
m.submodules.dec = self.dec
# set up instruction, pick fn unit
# no op: defaults to OP_ILLEGAL
comb += self.do_copy("insn_type", self.op_get("internal_op"))
- comb += self.do_copy("fn_unit", self.op_get("function_unit"))
+
+ #function unit for decoded instruction
+ fn = self.op_get("function_unit")
+ spr = Signal(10, reset_less=True)
+ comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
+
+ # for first test only forward SPR 18 to mmu
+ with m.If(self.dec.op.internal_op == MicrOp.OP_MTSPR):
+ with m.If((spr == 18) | (spr == 19)):
+ comb += self.do_copy("fn_unit",Function.MMU)
+ with m.Else():
+ comb += self.do_copy("fn_unit",fn)
+ with m.If(self.dec.op.internal_op == MicrOp.OP_MFSPR):
+ with m.If((spr == 18) | (spr == 19)):
+ comb += self.do_copy("fn_unit",Function.MMU)
+ with m.Else():
+ comb += self.do_copy("fn_unit",fn)
+ with m.Else():
+ comb += self.do_copy("fn_unit",fn)
# immediates
if self.needs_field("zero_a", "in1_sel"):
instructions are illegal (or privileged) or not, and instead of
just leaving at that, *replacing* the instruction to execute with
a suitable alternative (trap).
+
+ LDSTExceptions are done the cycle _after_ they're detected (after
+ they come out of LDSTCompUnit). basically despite the instruction
+ being decoded, the results of the decode are completely ignored
+ and "exception.happened" used to set the "actual" instruction to
+ "OP_TRAP". the LDSTException data structure gets filled in,
+ in the CompTrapOpSubset and that's what it fills in SRR.
+
+ to make this work, TestIssuer must notice "exception.happened"
+ after the (failed) LD/ST and copies the LDSTException info from
+ the output, into here (PowerDecoder2). without incrementing PC.
"""
+ def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None):
+ super().__init__(dec, opkls, fn_name, final, state)
+ self.exc = LDSTException("dec2_exc")
+
def get_col_subset(self, opkls):
subset = super().get_col_subset(opkls)
subset.add("in1_sel")
+ subset.add("asmcode")
subset.add("in2_sel")
subset.add("in3_sel")
subset.add("out_sel")
dec_irq_ok = Signal()
priv_ok = Signal()
illeg_ok = Signal()
+ exc = self.exc
comb += ext_irq_ok.eq(ext_irq & msr[MSR.EE]) # v3.0B p944 (MSR.EE)
- comb += dec_irq_ok.eq(dec_spr[63] & msr[MSR.EE]) # v3.0B 6.5.11 p1076
+ comb += dec_irq_ok.eq(dec_spr[63] & msr[MSR.EE]) # 6.5.11 p1076
comb += priv_ok.eq(is_priv_insn & msr[MSR.PR])
comb += illeg_ok.eq(op.internal_op == MicrOp.OP_ILLEGAL)
+ # LD/ST exceptions. TestIssuer copies the exception info at us
+ # after a failed LD/ST.
+ with m.If(exc.happened):
+ with m.If(exc.alignment):
+ self.trap(m, TT.PRIV, 0x600)
+ with m.Elif(exc.instr_fault):
+ with m.If(exc.segment_fault):
+ self.trap(m, TT.PRIV, 0x480)
+ with m.Else():
+ # pass exception info to trap to create SRR1
+ self.trap(m, TT.MEMEXC, 0x400, exc)
+ with m.Else():
+ with m.If(exc.segment_fault):
+ self.trap(m, TT.PRIV, 0x380)
+ with m.Else():
+ self.trap(m, TT.PRIV, 0x300)
+
# decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
- with m.If(dec_irq_ok):
+ with m.Elif(dec_irq_ok):
self.trap(m, TT.DEC, 0x900) # v3.0B 6.5 p1065
# external interrupt? only if MSR.EE set
comb += e_out.read_fast2.data.eq(FastRegs.SRR1) # constant: SRR1
comb += e_out.read_fast2.ok.eq(1)
+ # annoying simulator bug
+ if hasattr(e_out, "asmcode") and hasattr(self.dec.op, "asmcode"):
+ comb += e_out.asmcode.eq(self.dec.op.asmcode)
+
return m
- def trap(self, m, traptype, trapaddr):
+ def trap(self, m, traptype, trapaddr, exc=None):
"""trap: this basically "rewrites" the decoded instruction as a trap
"""
comb = m.d.comb
comb += self.do_copy("fn_unit", Function.TRAP, True)
comb += self.do_copy("trapaddr", trapaddr >> 4, True) # bottom 4 bits
comb += self.do_copy("traptype", traptype, True) # request type
+ comb += self.do_copy("ldst_exc", exc, True) # request type
comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state"
comb += self.do_copy("cia", self.state.pc, True) # copy of PC "state"
projects / soc.git / blobdiff