from nmutil.iocontrol import RecordObject
from nmutil.extend import exts
-from soc.decoder.power_regspec_map import regspec_decode
+from soc.decoder.power_regspec_map import regspec_decode_read
+from soc.decoder.power_regspec_map import regspec_decode_write
from soc.decoder.power_decoder import create_pdecode
from soc.decoder.power_enums import (InternalOp, CryIn, Function,
CRInSel, CROutSel,
LdstLen, In1Sel, In2Sel, In3Sel,
OutSel, SPR, RC)
+from soc.decoder.decode2execute1 import Decode2ToExecute1Type, Data
from soc.regfile.regfiles import FastRegs
+# see traptype (and trap main_stage.py)
+
+TT_FP = 1<<0
+TT_PRIV = 1<<1
+TT_TRAP = 1<<2
+TT_ADDR = 1<<3
+
+def decode_spr_num(spr):
+ return Cat(spr[5:10], spr[0:5])
+
+
+def instr_is_priv(m, op, insn):
+ """determines if the instruction is privileged or not
+ """
+ comb = m.d.comb
+ Signal = is_priv_insn(reset_less=True)
+ with m.Switch(op):
+ with m.Case(InternalOp.OP_ATTN) : comb += is_priv_insn.eq(1)
+ with m.Case(InternalOp.OP_MFMSR) : comb += is_priv_insn.eq(1)
+ with m.Case(InternalOp.OP_MTMSRD): comb += is_priv_insn.eq(1)
+ with m.Case(InternalOp.OP_RFID) : comb += is_priv_insn.eq(1)
+ with m.Case(InternalOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
+ with m.If(op == OP_MFSPR | op == OP_MTSPR):
+ with m.If(insn[20]): # field XFX.spr[-1] i think
+ comb += is_priv_insn.eq(1)
+ return is_priv_insn
+
+
class DecodeA(Elaboratable):
"""DecodeA from instruction
# MFSPR move from SPRs
with m.If(op.internal_op == InternalOp.OP_MFSPR):
- # XXX TODO: fast/slow SPR decoding and mapping
- comb += self.spr_out.data.eq(self.dec.SPR) # SPR field, XFX
- comb += self.spr_out.ok.eq(1)
+ spr = Signal(10, reset_less=True)
+ comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
+ with m.Switch(spr):
+ # fast SPRs
+ with m.Case(SPR.CTR.value):
+ comb += self.fast_out.data.eq(FastRegs.CTR)
+ comb += self.fast_out.ok.eq(1)
+ with m.Case(SPR.LR.value):
+ comb += self.fast_out.data.eq(FastRegs.LR)
+ comb += self.fast_out.ok.eq(1)
+ with m.Case(SPR.TAR.value):
+ comb += self.fast_out.data.eq(FastRegs.TAR)
+ comb += self.fast_out.ok.eq(1)
+ with m.Case(SPR.SRR0.value):
+ comb += self.fast_out.data.eq(FastRegs.SRR0)
+ comb += self.fast_out.ok.eq(1)
+ with m.Case(SPR.SRR1.value):
+ comb += self.fast_out.data.eq(FastRegs.SRR1)
+ comb += self.fast_out.ok.eq(1)
+ with m.Case(SPR.XER.value):
+ pass # do nothing
+ # XXX TODO: map to internal SPR numbers
+ # XXX TODO: dec and tb not to go through mapping.
+ with m.Default():
+ comb += self.spr_out.data.eq(spr)
+ comb += self.spr_out.ok.eq(1)
- return m
-
-
-class Data(Record):
-
- def __init__(self, width, name):
- name_ok = "%s_ok" % name
- layout = ((name, width), (name_ok, 1))
- Record.__init__(self, layout)
- self.data = getattr(self, name) # convenience
- self.ok = getattr(self, name_ok) # convenience
- self.data.reset_less = True # grrr
- self.reset_less = True # grrr
- def ports(self):
- return [self.data, self.ok]
+ return m
class DecodeB(Elaboratable):
comb += self.reg_out.data.eq(self.dec.RA)
comb += self.reg_out.ok.eq(1)
with m.Case(OutSel.SPR):
- comb += self.spr_out.data.eq(self.dec.SPR) # from XFX
- comb += self.spr_out.ok.eq(1)
+ spr = Signal(10, reset_less=True)
+ comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
# TODO MTSPR 1st spr (fast)
with m.If(op.internal_op == InternalOp.OP_MTSPR):
- pass
- """
- sprn := decode_spr_num(f_in.insn);
- v.ispr1 := fast_spr_num(sprn);
- -- Make slow SPRs single issue
- if is_fast_spr(v.ispr1) = '0' then
- v.decode.sgl_pipe := '1';
- -- send MMU-related SPRs to loadstore1
- case sprn is
- when SPR_DAR | SPR_DSISR | SPR_PID | SPR_PRTBL =>
- v.decode.unit := LDST;
- when others =>
- end case;
- end if;
- """
-
+ with m.Switch(spr):
+ # fast SPRs
+ with m.Case(SPR.CTR.value):
+ comb += self.fast_out.data.eq(FastRegs.CTR)
+ comb += self.fast_out.ok.eq(1)
+ with m.Case(SPR.LR.value):
+ comb += self.fast_out.data.eq(FastRegs.LR)
+ comb += self.fast_out.ok.eq(1)
+ with m.Case(SPR.TAR.value):
+ comb += self.fast_out.data.eq(FastRegs.TAR)
+ comb += self.fast_out.ok.eq(1)
+ with m.Case(SPR.SRR0.value):
+ comb += self.fast_out.data.eq(FastRegs.SRR0)
+ comb += self.fast_out.ok.eq(1)
+ with m.Case(SPR.SRR1.value):
+ comb += self.fast_out.data.eq(FastRegs.SRR1)
+ comb += self.fast_out.ok.eq(1)
+ with m.Case(SPR.XER.value):
+ pass # do nothing
+ # XXX TODO: map to internal SPR numbers
+ # XXX TODO: dec and tb not to go through mapping.
+ with m.Default():
+ comb += self.spr_out.data.eq(spr)
+ comb += self.spr_out.ok.eq(1)
# BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
op = self.dec.op
comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
comb += self.fast_out.ok.eq(1)
+ # TRAP fast1 = SRR0
+ with m.If(op.internal_op == InternalOp.OP_TRAP):
+ comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
+ comb += self.fast_out.ok.eq(1)
+
return m
comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
comb += self.fast_out.ok.eq(1)
+ # TRAP fast2 = SRR1
+ with m.If(op.internal_op == InternalOp.OP_TRAP):
+ comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
+ comb += self.fast_out.ok.eq(1)
+
return m
return [self.ca, self.ov, self.so]
-class Decode2ToExecute1Type(RecordObject):
-
- def __init__(self, name=None):
-
- RecordObject.__init__(self, name=name)
-
- self.valid = Signal(reset_less=True)
- self.insn_type = Signal(InternalOp, reset_less=True)
- self.fn_unit = Signal(Function, reset_less=True)
- self.nia = Signal(64, reset_less=True)
- self.write_reg = Data(5, name="rego")
- self.write_ea = Data(5, name="ea") # for LD/ST in update mode
- self.read_reg1 = Data(5, name="reg1")
- self.read_reg2 = Data(5, name="reg2")
- self.read_reg3 = Data(5, name="reg3")
- self.imm_data = Data(64, name="imm")
- self.write_spr = Data(10, name="spro")
- self.read_spr1 = Data(10, name="spr1")
- self.read_spr2 = Data(10, name="spr2")
-
- self.read_fast1 = Data(3, name="fast1")
- self.read_fast2 = Data(3, name="fast2")
- self.write_fast1 = Data(3, name="fasto1")
- self.write_fast2 = Data(3, name="fasto2")
-
- self.read_cr1 = Data(3, name="cr_in1")
- self.read_cr2 = Data(3, name="cr_in2")
- self.read_cr3 = Data(3, name="cr_in2")
- self.read_cr_whole = Signal(reset_less=True)
- self.write_cr = Data(3, name="cr_out")
- self.write_cr_whole = Signal(reset_less=True)
- self.lk = Signal(reset_less=True)
- self.rc = Data(1, "rc")
- self.oe = Data(1, "oe")
- self.invert_a = Signal(reset_less=True)
- self.zero_a = Signal(reset_less=True)
- self.invert_out = Signal(reset_less=True)
- self.input_carry = Signal(CryIn, reset_less=True)
- self.output_carry = Signal(reset_less=True)
- self.input_cr = Signal(reset_less=True) # instr. has a CR as input
- self.output_cr = Signal(reset_less=True) # instr. has a CR as output
- self.is_32bit = Signal(reset_less=True)
- self.is_signed = Signal(reset_less=True)
- self.insn = Signal(32, reset_less=True)
- self.data_len = Signal(4, reset_less=True) # bytes
- self.byte_reverse = Signal(reset_less=True)
- self.sign_extend = Signal(reset_less=True)# do we need this?
- self.update = Signal(reset_less=True) # LD/ST is "update" variant
-
-
class PowerDecode2(Elaboratable):
def __init__(self, dec):
comb += dec_cr_out.sel_in.eq(op.cr_out)
comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
- # decode LD/ST length
- with m.Switch(op.ldst_len):
- with m.Case(LdstLen.is1B):
- comb += e.data_len.eq(1)
- with m.Case(LdstLen.is2B):
- comb += e.data_len.eq(2)
- with m.Case(LdstLen.is4B):
- comb += e.data_len.eq(4)
- with m.Case(LdstLen.is8B):
- comb += e.data_len.eq(8)
comb += e.nia.eq(0) # XXX TODO (or remove? not sure yet)
fu = op.function_unit
comb += e.write_cr_whole.eq(dec_cr_out.whole_reg)
# decoded/selected instruction flags
+ comb += e.data_len.eq(op.ldst_len)
comb += e.invert_a.eq(op.inv_a)
comb += e.invert_out.eq(op.inv_out)
comb += e.input_carry.eq(op.cry_in) # carry comes in
comb += e.input_cr.eq(op.cr_in) # condition reg comes in
comb += e.output_cr.eq(op.cr_out) # condition reg goes in
+ # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
+ with m.If(op.internal_op == InternalOp.OP_TRAP):
+ comb += e.trapaddr.eq(0x70) # addr=0x700 (strip first nibble)
+
+ return m
+ # privileged instruction
+ with m.If(instr_is_priv(m, op.internal_op, e.insn) & msr[MSR_PR]):
+ # don't request registers RA/RT
+ comb += e.read_reg1.eq(0)
+ comb += e.read_reg2.eq(0)
+ comb += e.read_reg3.eq(0)
+ comb += e.write_reg.eq(0)
+ comb += e.write_ea.eq(0)
+ # privileged instruction trap
+ comb += op.internal_op.eq(InternalOp.OP_TRAP)
+ comb += e.traptype.eq(TT_PRIV) # request privileged instruction
+ comb += e.trapaddr.eq(0x70) # addr=0x700 (strip first nibble)
return m
- def regspecmap(self, regfile, regname):
- """regspecmap: provides PowerDecode2 with an encoding relationship
+ def regspecmap_read(self, regfile, regname):
+ """regspecmap_read: provides PowerDecode2 with an encoding relationship
to Function Unit port regfiles (read-enable, read regnum, write regnum)
regfile and regname arguments are fields 1 and 2 from a given regspec.
"""
- return regspec_decode(self.e, regfile, regname)
+ return regspec_decode_read(self.e, regfile, regname)
+
+ def regspecmap_write(self, regfile, regname):
+ """regspecmap_write: provides PowerDecode2 with an encoding relationship
+ to Function Unit port regfiles (write port, write regnum)
+ regfile and regname arguments are fields 1 and 2 from a given regspec.
+ """
+ return regspec_decode_write(self.e, regfile, regname)
def rdflags(self, cu):
rdl = []
for idx in range(cu.n_src):
regfile, regname, _ = cu.get_in_spec(idx)
- rdflag, read, write = self.regspecmap(regfile, regname)
+ rdflag, read = self.regspecmap_read(regfile, regname)
rdl.append(rdflag)
print ("rdflags", rdl)
return Cat(*rdl)
projects / soc.git / blobdiff