sorting out trap fastregs

[soc.git] / src / soc / decoder / power_decoder2.py

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index aa9fcaecae14b6bf38099e153dd9bf0aa0276fdb..1830c5f73e91b47a691c3c8d45bb97182ac7e1b0 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -312,6 +312,11 @@ class DecodeOut(Elaboratable):
             comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
             comb += self.fast_out.ok.eq(1)
 
+        # TRAP fast1 = SRR0
+        with m.If(op.internal_op == InternalOp.OP_TRAP):
+            comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
+            comb += self.fast_out.ok.eq(1)
+
         return m
 
 
@@ -351,6 +356,11 @@ class DecodeOut2(Elaboratable):
                 comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
                 comb += self.fast_out.ok.eq(1)
 
+        # TRAP fast2 = SRR1
+        with m.If(op.internal_op == InternalOp.OP_TRAP):
+            comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
+            comb += self.fast_out.ok.eq(1)
+
         return m
 
 
@@ -587,7 +597,7 @@ class PowerDecode2(Elaboratable):
         comb += e.read_fast1.eq(dec_a.fast_out)
         comb += e.read_fast2.eq(dec_b.fast_out)
         comb += e.write_fast1.eq(dec_o.fast_out)
-        comb += e.write_fast1.eq(dec_o2.fast_out)
+        comb += e.write_fast2.eq(dec_o2.fast_out)
 
         comb += e.read_cr1.eq(dec_cr_in.cr_bitfield)
         comb += e.read_cr2.eq(dec_cr_in.cr_bitfield_b)