from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
from nmigen.cli import rtlil
+from nmutil.util import sel
+
from soc.regfile.regfiles import XERRegs
from nmutil.picker import PriorityPicker
from soc.experiment.mem_types import LDSTException
+from soc.decoder.power_svp64_prefix import SVP64PrefixDecoder
+from soc.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
from soc.decoder.power_regspec_map import regspec_decode_read
from soc.decoder.power_regspec_map import regspec_decode_write
from soc.decoder.power_decoder import create_pdecode
from soc.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
Decode2ToOperand)
from soc.sv.svp64 import SVP64Rec
-from soc.consts import MSR
+from soc.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field,
+ SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs)
from soc.regfile.regfiles import FastRegs
from soc.consts import TT
with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
MicrOp.OP_MTMSR, MicrOp.OP_RFID):
comb += is_priv_insn.eq(1)
- # XXX TODO
- #with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
+ with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):
with m.If(insn[20]): # field XFX.spr[-1] i think
comb += is_priv_insn.eq(1)
return m
-class SVP64RegExtra(Elaboratable):
- """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
-
- incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
- depending on info in one of the positions in the EXTRA field.
-
- designed so that "no change" to the 5-bit register number occurs if
- SV either does not apply or the relevant EXTRA2/3 field bits are zero.
-
- see https://libre-soc.org/openpower/sv/svp64/
- """
- def __init__(self):
- self.extra = Signal(10, reset_less=True)
- self.etype = Signal(SVEtype, reset_less=True) # 2 or 3 bits
- self.idx = Signal(SVEXTRA, reset_less=True) # which part of extra
- self.reg_in = Signal(5) # incoming reg number (5 bits, RA, RB)
- self.reg_out = Signal(7) # extra-augmented output (7 bits)
- self.isvec = Signal(1) # reg is marked as vector if true
-
- def elaborate(self, platform):
- m = Module()
- comb = m.d.comb
-
- # first get the spec. if not changed it's "scalar identity behaviour"
- # which is zero which is ok.
- spec = Signal(3)
-
- # back in the LDSTRM-* and RM-* files generated by sv_analysis.py
- # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
- # which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
- # the register-extension information. extract those how
- with m.Switch(self.etype):
- # 2-bit index selection mode
- with m.Case(SVEtype.EXTRA2):
- with m.Switch(self.idx):
- with m.Case(SVEXTRA.Idx0): # 1st 2 bits
- comb += spec[1:3].eq(self.extra[0:2])
- with m.Case(SVEXTRA.Idx1): # 2nd 2 bits
- comb += spec[1:3].eq(self.extra[2:4])
- with m.Case(SVEXTRA.Idx2): # 3rd 2 bits
- comb += spec[1:3].eq(self.extra[4:6])
- with m.Case(SVEXTRA.Idx3): # 4th 2 bits
- comb += spec[1:3].eq(self.extra[6:8])
- # 3-bit index selection mode
- with m.Case(SVEtype.EXTRA3):
- with m.Switch(self.idx):
- with m.Case(SVEXTRA.Idx0): # 1st 3 bits
- comb += spec.eq(self.extra[0:3])
- with m.Case(SVEXTRA.Idx1): # 2nd 3 bits
- comb += spec.eq(self.extra[3:6])
- with m.Case(SVEXTRA.Idx2): # 3rd 3 bits
- comb += spec.eq(self.extra[6:9])
- # cannot fit more than 9 bits so there is no 4th thing
-
- # now decode it. bit 2 is "scalar/vector". note that spec could be zero
- # from above, which (by design) has the effect of "no change", below.
-
- # simple: isvec is top bit of spec
- comb += self.isvec.eq(spec[2])
-
- # decode vector differently from scalar
- with m.If(self.isvec):
- # Vector: shifted up, extra in LSBs (RA << 2) | spec[0:1]
- comb += self.reg_out.eq(Cat(spec[:2], self.reg_in))
- with m.Else():
- # Scalar: not shifted up, extra in MSBs RA | (spec[0:1] << 5)
- comb += self.reg_out.eq(Cat(self.reg_in, spec[:2]))
-
- return m
-
-
class DecodeA(Elaboratable):
"""DecodeA from instruction
def __init__(self, dec):
self.dec = dec
- self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(In1Sel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(7, name="reg_a")
- self.reg_isvec = Signal(1, name="reg_a_isvec") # TODO: in reg_out
+ self.reg_out = Data(5, name="reg_a")
self.spr_out = Data(SPR, "spr_a")
self.fast_out = Data(3, "fast_a")
m = Module()
comb = m.d.comb
op = self.dec.op
+ reg = self.reg_out
m.submodules.sprmap = sprmap = SPRMap()
- m.submodules.svdec = svdec = SVP64RegExtra()
-
- # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
- reg = Signal(5, reset_less=True)
# select Register A field
ra = Signal(5, reset_less=True)
with m.If((self.sel_in == In1Sel.RA) |
((self.sel_in == In1Sel.RA_OR_ZERO) &
(ra != Const(0, 5)))):
- comb += reg.eq(ra)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(ra)
+ comb += reg.ok.eq(1)
# some Logic/ALU ops have RS as the 3rd arg, but no "RA".
# moved it to 1st position (in1_sel)... because
rs = Signal(5, reset_less=True)
comb += rs.eq(self.dec.RS)
with m.If(self.sel_in == In1Sel.RS):
- comb += reg.eq(rs)
- comb += self.reg_out.ok.eq(1)
-
- # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
- # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
- # which in turn were auto-generated by sv_analysis.py
-
- extra = self.sv_rm.extra # SVP64 extra bits 10:18
- comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
- comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
- comb += svdec.idx.eq(op.sv_in1) # SVP64 reg #1 (matches in1_sel)
- comb += svdec.reg_in.eq(reg) # 5-bit (RA, RS)
-
- # outputs: 7-bit reg number and whether it's vectorised
- comb += self.reg_out.data.eq(svdec.reg_out)
- comb += self.reg_isvec.eq(svdec.isvec)
+ comb += reg.data.eq(rs)
+ comb += reg.ok.eq(1)
# decode Fast-SPR based on instruction type
with m.Switch(op.internal_op):
def __init__(self, dec):
self.dec = dec
- self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(In2Sel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(5, "reg_b")
+ self.reg_out = Data(7, "reg_b")
self.reg_isvec = Signal(1, name="reg_b_isvec") # TODO: in reg_out
self.fast_out = Data(3, "fast_b")
m = Module()
comb = m.d.comb
op = self.dec.op
- m.submodules.svdec = svdec = SVP64RegExtra()
-
- # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
- reg = Signal(5, reset_less=True)
+ reg = self.reg_out
# select Register B field
with m.Switch(self.sel_in):
with m.Case(In2Sel.RB):
- comb += reg.eq(self.dec.RB)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RB)
+ comb += reg.ok.eq(1)
with m.Case(In2Sel.RS):
# for M-Form shiftrot
- comb += reg.eq(self.dec.RS)
- comb += self.reg_out.ok.eq(1)
-
- # now do the SVP64 munging. different from DecodeA only by sv_in2
-
- extra = self.sv_rm.extra # SVP64 extra bits 10:18
- comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
- comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
- comb += svdec.idx.eq(op.sv_in2) # SVP64 reg #2 (matches in2_sel)
- comb += svdec.reg_in.eq(reg) # 5-bit (RA, RS)
-
- # outputs: 7-bit reg number and whether it's vectorised
- comb += self.reg_out.data.eq(svdec.reg_out)
- comb += self.reg_isvec.eq(svdec.isvec)
+ comb += reg.data.eq(self.dec.RS)
+ comb += reg.ok.eq(1)
# decode SPR2 based on instruction type
# BCREG implicitly uses LR or TAR for 2nd reg
def __init__(self, dec):
self.dec = dec
- self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(In3Sel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
self.reg_out = Data(5, "reg_c")
- self.reg_isvec = Signal(1, name="reg_c_isvec") # TODO: in reg_out
def elaborate(self, platform):
m = Module()
comb = m.d.comb
op = self.dec.op
- m.submodules.svdec = svdec = SVP64RegExtra()
-
- # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
- reg = Signal(5, reset_less=True)
+ reg = self.reg_out
# select Register C field
with m.Switch(self.sel_in):
with m.Case(In3Sel.RB):
# for M-Form shiftrot
- comb += reg.eq(self.dec.RB)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RB)
+ comb += reg.ok.eq(1)
with m.Case(In3Sel.RS):
- comb += reg.eq(self.dec.RS)
- comb += self.reg_out.ok.eq(1)
-
- # now do the SVP64 munging. different from DecodeA only by sv_in3
-
- extra = self.sv_rm.extra # SVP64 extra bits 10:18
- comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
- comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
- comb += svdec.idx.eq(op.sv_in3) # SVP64 reg #3 (matches in3_sel)
- comb += svdec.reg_in.eq(reg) # 5-bit (RA, RS)
-
- # outputs: 7-bit reg number and whether it's vectorised
- comb += self.reg_out.data.eq(svdec.reg_out)
- comb += self.reg_isvec.eq(svdec.isvec)
+ comb += reg.data.eq(self.dec.RS)
+ comb += reg.ok.eq(1)
return m
def __init__(self, dec):
self.dec = dec
- self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(OutSel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
self.reg_out = Data(5, "reg_o")
- self.reg_isvec = Signal(1, name="reg_c_isvec") # TODO: in reg_out
self.spr_out = Data(SPR, "spr_o")
self.fast_out = Data(3, "fast_o")
comb = m.d.comb
m.submodules.sprmap = sprmap = SPRMap()
op = self.dec.op
- m.submodules.svdec = svdec = SVP64RegExtra()
-
- # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
- reg = Signal(5, reset_less=True)
+ reg = self.reg_out
# select Register out field
with m.Switch(self.sel_in):
with m.Case(OutSel.RT):
- comb += reg.eq(self.dec.RT)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RT)
+ comb += reg.ok.eq(1)
with m.Case(OutSel.RA):
- comb += reg.eq(self.dec.RA)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RA)
+ comb += reg.ok.eq(1)
with m.Case(OutSel.SPR):
spr = Signal(10, reset_less=True)
comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
comb += self.spr_out.eq(sprmap.spr_o)
comb += self.fast_out.eq(sprmap.fast_o)
- # now do the SVP64 munging. different from DecodeA only by sv_out
-
- extra = self.sv_rm.extra # SVP64 extra bits 10:18
- comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
- comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
- comb += svdec.idx.eq(op.sv_out) # SVP64 reg out1 (matches out_sel)
- comb += svdec.reg_in.eq(reg) # 5-bit (RA, RS)
-
- # outputs: 7-bit reg number and whether it's vectorised
- comb += self.reg_out.data.eq(svdec.reg_out)
- comb += self.reg_isvec.eq(svdec.isvec)
-
# determine Fast Reg
with m.Switch(op.internal_op):
class DecodeOut2(Elaboratable):
"""DecodeOut2 from instruction
- decodes output registers.
+ decodes output registers (2nd one). note that RA is *implicit* below,
+ which now causes problems with SVP64
TODO: SVP64 is a little more complex, here. svp64 allows extending
by one more destination by having one more EXTRA field. RA-as-src
def __init__(self, dec):
self.dec = dec
- self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(OutSel, reset_less=True)
self.lk = Signal(reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(5, "reg_o")
- self.fast_out = Data(3, "fast_o")
+ self.reg_out = Data(5, "reg_o2")
+ self.fast_out = Data(3, "fast_o2")
def elaborate(self, platform):
m = Module()
comb = m.d.comb
+ op = self.dec.op
+ #m.submodules.svdec = svdec = SVP64RegExtra()
+
+ # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
+ #reg = Signal(5, reset_less=True)
if hasattr(self.dec.op, "upd"):
# update mode LD/ST uses read-reg A also as an output
with m.If(self.dec.op.upd == LDSTMode.update):
- comb += self.reg_out.eq(self.dec.RA)
+ comb += self.reg_out.data.eq(self.dec.RA)
comb += self.reg_out.ok.eq(1)
# B, BC or BCREG: potential implicit register (LR) output
# these give bl, bcl, bclrl, etc.
- op = self.dec.op
with m.Switch(op.internal_op):
# BC* implicit register (LR)
def __init__(self, dec):
self.dec = dec
- self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(CRInSel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
self.cr_bitfield = Data(3, "cr_bitfield")
self.cr_bitfield_b = Data(3, "cr_bitfield_b")
self.cr_bitfield_o = Data(3, "cr_bitfield_o")
self.whole_reg = Data(8, "cr_fxm")
+ self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
def elaborate(self, platform):
m = Module()
- m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
- reverse_o=True)
-
comb = m.d.comb
op = self.dec.op
+ m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
+ reverse_o=True)
+ # zero-initialisation
comb += self.cr_bitfield.ok.eq(0)
comb += self.cr_bitfield_b.ok.eq(0)
+ comb += self.cr_bitfield_o.ok.eq(0)
comb += self.whole_reg.ok.eq(0)
+ comb += self.sv_override.eq(0)
+
+ # select the relevant CR bitfields
with m.Switch(self.sel_in):
with m.Case(CRInSel.NONE):
pass # No bitfield activated
with m.Case(CRInSel.CR0):
comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
comb += self.cr_bitfield.ok.eq(1)
+ comb += self.sv_override.eq(1)
+ with m.Case(CRInSel.CR1):
+ comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
+ comb += self.cr_bitfield.ok.eq(1)
+ comb += self.sv_override.eq(2)
with m.Case(CRInSel.BI):
comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
comb += self.cr_bitfield.ok.eq(1)
def __init__(self, dec):
self.dec = dec
- self.sv_rm = SVP64Rec() # SVP64 RM field
self.rc_in = Signal(reset_less=True)
self.sel_in = Signal(CROutSel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
self.cr_bitfield = Data(3, "cr_bitfield")
self.whole_reg = Data(8, "cr_fxm")
+ self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
def elaborate(self, platform):
m = Module()
comb += self.cr_bitfield.ok.eq(0)
comb += self.whole_reg.ok.eq(0)
+ comb += self.sv_override.eq(0)
+
+ # please note these MUST match (setting of cr_bitfield.ok) exactly
+ # with write_cr0 below in PowerDecoder2. the reason it's separated
+ # is to avoid having duplicate copies of DecodeCROut in multiple
+ # PowerDecoderSubsets. register decoding should be a one-off in
+ # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
+
with m.Switch(self.sel_in):
with m.Case(CROutSel.NONE):
pass # No bitfield activated
with m.Case(CROutSel.CR0):
comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
+ comb += self.sv_override.eq(1)
+ with m.Case(CROutSel.CR1):
+ comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
+ comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
+ comb += self.sv_override.eq(2)
with m.Case(CROutSel.BF):
comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
comb += self.cr_bitfield.ok.eq(1)
only fields actually requested are copied over. hence, "subset" (duh).
"""
- def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None):
+ def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None,
+ svp64_en=True):
- self.sv_rm = SVP64Rec(name="dec_svp64") # SVP64 RM field
+ self.svp64_en = svp64_en
+ if svp64_en:
+ self.sv_rm = SVP64Rec(name="dec_svp64") # SVP64 RM field
self.final = final
self.opkls = opkls
self.fn_name = fn_name
self.state = state
def get_col_subset(self, do):
- subset = {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
+ subset = { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
for k, v in record_names.items():
if hasattr(do, k):
subset.add(v)
return subset
def rowsubsetfn(self, opcode, row):
- return row['unit'] == self.fn_name
+ """select per-Function-Unit subset of opcodes to be processed
+
+ normally this just looks at the "unit" column. MMU is different
+ in that it processes specific SPR set/get operations that the SPR
+ pipeline should not.
+ """
+ return (row['unit'] == self.fn_name or
+ # sigh a dreadful hack: MTSPR and MFSPR need to be processed
+ # by the MMU pipeline so we direct those opcodes to MMU **AND**
+ # SPR pipelines, then selectively weed out the SPRs that should
+ # or should not not go to each pipeline, further down.
+ # really this should be done by modifying the CSV syntax
+ # to support multiple tasks (unit column multiple entries)
+ # see https://bugs.libre-soc.org/show_bug.cgi?id=310
+ (self.fn_name == 'MMU' and row['unit'] == 'SPR' and
+ row['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
+ )
def ports(self):
- return self.dec.ports() + self.e.ports() + self.sv_rm.ports()
+ ports = self.dec.ports() + self.e.ports()
+ if self.svp64_en:
+ ports += self.sv_rm.ports()
+ return ports
def needs_field(self, field, op_field):
if self.final:
state = self.state
op, do = self.dec.op, self.do
msr, cia = state.msr, state.pc
-
# fill in for a normal instruction (not an exception)
# copy over if non-exception, non-privileged etc. is detected
if not self.final:
# set up submodule decoders
m.submodules.dec = self.dec
- m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
+ m.submodules.dec_rc = self.dec_rc = dec_rc = DecodeRC(self.dec)
m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
- m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec)
- m.submodules.dec_cr_out = self.dec_cr_out = DecodeCROut(self.dec)
# copy instruction through...
- for i in [do.insn,
- dec_rc.insn_in, dec_oe.insn_in,
- self.dec_cr_in.insn_in, self.dec_cr_out.insn_in]:
+ for i in [do.insn, dec_rc.insn_in, dec_oe.insn_in, ]:
comb += i.eq(self.dec.opcode_in)
# ...and subdecoders' input fields
comb += dec_rc.sel_in.eq(op.rc_sel)
comb += dec_oe.sel_in.eq(op.rc_sel) # XXX should be OE sel
- comb += self.dec_cr_in.sel_in.eq(op.cr_in)
- comb += self.dec_cr_in.sv_rm.eq(self.sv_rm)
- comb += self.dec_cr_out.sv_rm.eq(self.sv_rm)
- comb += self.dec_cr_out.sel_in.eq(op.cr_out)
- comb += self.dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
# copy "state" over
comb += self.do_copy("msr", msr)
# set up instruction type
# no op: defaults to OP_ILLEGAL
- comb += self.do_copy("insn_type", self.op_get("internal_op"))
+ internal_op = self.op_get("internal_op")
+ comb += self.do_copy("insn_type", internal_op)
# function unit for decoded instruction: requires minor redirect
# for SPR set/get
spr = Signal(10, reset_less=True)
comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
- # for first test only forward SPRs 18 and 19 to MMU, when
- # operation is MTSPR or MFSPR. TODO: add other MMU SPRs
- with m.If(((self.dec.op.internal_op == MicrOp.OP_MTSPR) |
- (self.dec.op.internal_op == MicrOp.OP_MFSPR)) &
- ((spr == SPR.DSISR) | (spr == SPR.DAR))):
- comb += self.do_copy("fn_unit", Function.MMU)
+ # Microwatt doesn't implement the partition table
+ # instead has PRTBL register (SPR) to point to process table
+ is_spr_mv = Signal()
+ is_mmu_spr = Signal()
+ comb += is_spr_mv.eq((internal_op == MicrOp.OP_MTSPR) |
+ (internal_op == MicrOp.OP_MFSPR))
+ comb += is_mmu_spr.eq((spr == SPR.DSISR.value) |
+ (spr == SPR.DAR.value) |
+ (spr == SPR.PRTBL.value) |
+ (spr == SPR.PIDR.value))
+ # MMU must receive MMU SPRs
+ with m.If(is_spr_mv & (fn == Function.SPR) & is_mmu_spr):
+ comb += self.do_copy("fn_unit", Function.NONE)
+ comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)
+ # SPR pipe must *not* receive MMU SPRs
+ with m.Elif(is_spr_mv & (fn == Function.MMU) & ~is_mmu_spr):
+ comb += self.do_copy("fn_unit", Function.NONE)
+ comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)
+ # all others ok
with m.Else():
- comb += self.do_copy("fn_unit",fn)
+ comb += self.do_copy("fn_unit", fn)
# immediates
if self.needs_field("zero_a", "in1_sel"):
comb += self.do_copy("rc", dec_rc.rc_out)
comb += self.do_copy("oe", dec_oe.oe_out)
- # CR in/out
- comb += self.do_copy("read_cr_whole", self.dec_cr_in.whole_reg)
- comb += self.do_copy("write_cr_whole", self.dec_cr_out.whole_reg)
- comb += self.do_copy("write_cr0", self.dec_cr_out.cr_bitfield.ok)
+ # CR in/out - note: these MUST match with what happens in
+ # DecodeCROut!
+ rc_out = self.dec_rc.rc_out.data
+ with m.Switch(op.cr_out):
+ with m.Case(CROutSel.CR0, CROutSel.CR1):
+ comb += self.do_copy("write_cr0", rc_out) # only when RC=1
+ with m.Case(CROutSel.BF, CROutSel.BT):
+ comb += self.do_copy("write_cr0", 1)
comb += self.do_copy("input_cr", self.op_get("cr_in")) # CR in
comb += self.do_copy("output_cr", self.op_get("cr_out")) # CR out
the output, into here (PowerDecoder2). without incrementing PC.
"""
- def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None):
- super().__init__(dec, opkls, fn_name, final, state)
+ def __init__(self, dec, opkls=None, fn_name=None, final=False,
+ state=None, svp64_en=True):
+ super().__init__(dec, opkls, fn_name, final, state, svp64_en)
self.exc = LDSTException("dec2_exc")
+ if self.svp64_en:
+ self.cr_out_isvec = Signal(1, name="cr_out_isvec")
+ self.cr_in_isvec = Signal(1, name="cr_in_isvec")
+ self.cr_in_b_isvec = Signal(1, name="cr_in_b_isvec")
+ self.cr_in_o_isvec = Signal(1, name="cr_in_o_isvec")
+ self.in1_isvec = Signal(1, name="reg_a_isvec")
+ self.in2_isvec = Signal(1, name="reg_b_isvec")
+ self.in3_isvec = Signal(1, name="reg_c_isvec")
+ self.o_isvec = Signal(1, name="reg_o_isvec")
+ self.o2_isvec = Signal(1, name="reg_o2_isvec")
+ self.no_in_vec = Signal(1, name="no_in_vec") # no inputs vector
+ self.no_out_vec = Signal(1, name="no_out_vec") # no outputs vector
+ else:
+ self.no_in_vec = Const(1, 1)
+ self.no_out_vec = Const(1, 1)
+
def get_col_subset(self, opkls):
subset = super().get_col_subset(opkls)
subset.add("asmcode")
subset.add("in2_sel")
subset.add("in3_sel")
subset.add("out_sel")
- subset.add("sv_in1")
- subset.add("sv_in2")
- subset.add("sv_in3")
- subset.add("sv_out")
- subset.add("SV_Etype")
- subset.add("SV_Ptype")
+ if self.svp64_en:
+ subset.add("sv_in1")
+ subset.add("sv_in2")
+ subset.add("sv_in3")
+ subset.add("sv_out")
+ subset.add("sv_cr_in")
+ subset.add("sv_cr_out")
+ subset.add("SV_Etype")
+ subset.add("SV_Ptype")
subset.add("lk")
subset.add("internal_op")
subset.add("form")
state = self.state
e_out, op, do_out = self.e, self.dec.op, self.e.do
dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
+ rc_out = self.dec_rc.rc_out.data
e = self.e_tmp
do = e.do
m.submodules.dec_c = dec_c = DecodeC(self.dec)
m.submodules.dec_o = dec_o = DecodeOut(self.dec)
m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
+ m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec)
+ m.submodules.dec_cr_out = self.dec_cr_out = DecodeCROut(self.dec)
+
+ if self.svp64_en:
+ # and SVP64 Extra decoders
+ m.submodules.crout_svdec = crout_svdec = SVP64CRExtra()
+ m.submodules.crin_svdec = crin_svdec = SVP64CRExtra()
+ m.submodules.crin_svdec_b = crin_svdec_b = SVP64CRExtra()
+ m.submodules.crin_svdec_o = crin_svdec_o = SVP64CRExtra()
+ m.submodules.in1_svdec = in1_svdec = SVP64RegExtra()
+ m.submodules.in2_svdec = in2_svdec = SVP64RegExtra()
+ m.submodules.in3_svdec = in3_svdec = SVP64RegExtra()
+ m.submodules.o_svdec = o_svdec = SVP64RegExtra()
+ m.submodules.o2_svdec = o2_svdec = SVP64RegExtra()
+
+ # debug access to crout_svdec (used in get_pdecode_cr_out)
+ self.crout_svdec = crout_svdec
+
+ # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
+ reg = Signal(5, reset_less=True)
# copy instruction through...
for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
+ self.dec_cr_in.insn_in, self.dec_cr_out.insn_in,
dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]:
comb += i.eq(self.dec.opcode_in)
- # ... and svp64 rm
- for i in [dec_a.insn_in, dec_b.insn_in,
- dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]:
- comb += i.eq(self.sv_rm)
+ # CR setup
+ comb += self.dec_cr_in.sel_in.eq(op.cr_in)
+ comb += self.dec_cr_out.sel_in.eq(op.cr_out)
+ comb += self.dec_cr_out.rc_in.eq(rc_out)
+
+ # CR register info
+ comb += self.do_copy("read_cr_whole", self.dec_cr_in.whole_reg)
+ comb += self.do_copy("write_cr_whole", self.dec_cr_out.whole_reg)
# ...and subdecoders' input fields
comb += dec_a.sel_in.eq(op.in1_sel)
if hasattr(do, "lk"):
comb += dec_o2.lk.eq(do.lk)
- # registers a, b, c and out and out2 (LD/ST EA)
- for to_reg, fromreg in (
- (e.read_reg1, dec_a.reg_out),
- (e.read_reg2, dec_b.reg_out),
- (e.read_reg3, dec_c.reg_out),
- (e.write_reg, dec_o.reg_out),
- (e.write_ea, dec_o2.reg_out)):
- comb += to_reg.data.eq(fromreg.data)
- comb += to_reg.ok.eq(fromreg.ok)
+ if self.svp64_en:
+ # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
+ # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
+ # which in turn were auto-generated by sv_analysis.py
+ extra = self.sv_rm.extra # SVP64 extra bits 10:18
+
+ #######
+ # CR out
+ comb += crout_svdec.idx.eq(op.sv_cr_out) # SVP64 CR out
+ comb += self.cr_out_isvec.eq(crout_svdec.isvec)
+
+ #######
+ # CR in - selection slightly different due to shared CR field sigh
+ cr_a_idx = Signal(SVEXTRA)
+ cr_b_idx = Signal(SVEXTRA)
+
+ # these change slightly, when decoding BA/BB. really should have
+ # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
+ comb += cr_a_idx.eq(op.sv_cr_in)
+ comb += cr_b_idx.eq(SVEXTRA.NONE)
+ with m.If(op.sv_cr_in == SVEXTRA.Idx_1_2.value):
+ comb += cr_a_idx.eq(SVEXTRA.Idx1)
+ comb += cr_b_idx.eq(SVEXTRA.Idx2)
+
+ comb += self.cr_in_isvec.eq(crin_svdec.isvec)
+ comb += self.cr_in_b_isvec.eq(crin_svdec_b.isvec)
+ comb += self.cr_in_o_isvec.eq(crin_svdec_o.isvec)
+
+ # indices are slightly different, BA/BB mess sorted above
+ comb += crin_svdec.idx.eq(cr_a_idx) # SVP64 CR in A
+ comb += crin_svdec_b.idx.eq(cr_b_idx) # SVP64 CR in B
+ comb += crin_svdec_o.idx.eq(op.sv_cr_out) # SVP64 CR out
+
+ # get SVSTATE srcstep (TODO: elwidth, dststep etc.) needed below
+ srcstep = Signal.like(self.state.svstate.srcstep)
+ comb += srcstep.eq(self.state.svstate.srcstep)
+
+ # registers a, b, c and out and out2 (LD/ST EA)
+ for to_reg, fromreg, svdec in (
+ (e.read_reg1, dec_a.reg_out, in1_svdec),
+ (e.read_reg2, dec_b.reg_out, in2_svdec),
+ (e.read_reg3, dec_c.reg_out, in3_svdec),
+ (e.write_reg, dec_o.reg_out, o_svdec),
+ (e.write_ea, dec_o2.reg_out, o2_svdec)):
+ comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
+ comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
+ comb += svdec.reg_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
+ comb += to_reg.ok.eq(fromreg.ok)
+ # detect if Vectorised: add srcstep if yes. TODO: a LOT.
+ # this trick only holds when elwidth=default and in single-pred
+ with m.If(svdec.isvec):
+ comb += to_reg.data.eq(srcstep+svdec.reg_out) # 7-bit output
+ with m.Else():
+ comb += to_reg.data.eq(svdec.reg_out) # 7-bit output
+
+ comb += in1_svdec.idx.eq(op.sv_in1) # SVP64 reg #1 (in1_sel)
+ comb += in2_svdec.idx.eq(op.sv_in2) # SVP64 reg #2 (in2_sel)
+ comb += in3_svdec.idx.eq(op.sv_in3) # SVP64 reg #3 (in3_sel)
+ comb += o_svdec.idx.eq(op.sv_out) # SVP64 output (out_sel)
+ # XXX TODO - work out where this should come from. the problem is
+ # that LD-with-update is implied (computed from "is instruction in
+ # "update mode" rather than specified cleanly as its own CSV column
+ #comb += o2_svdec.idx.eq(op.sv_out) # SVP64 output (implicit)
+
+ # output reg-is-vectorised (and when no in/out is vectorised)
+ comb += self.in1_isvec.eq(in1_svdec.isvec)
+ comb += self.in2_isvec.eq(in2_svdec.isvec)
+ comb += self.in3_isvec.eq(in3_svdec.isvec)
+ comb += self.o_isvec.eq(o_svdec.isvec)
+ comb += self.o2_isvec.eq(o2_svdec.isvec)
+ # TODO add SPRs here. must be True when *all* are scalar
+ l = map(lambda svdec: svdec.isvec, [in1_svdec, in2_svdec, in3_svdec,
+ crin_svdec, crin_svdec_b, crin_svdec_o])
+ comb += self.no_in_vec.eq(~Cat(*l).bool()) # all input scalar
+ l = map(lambda svdec: svdec.isvec, [o2_svdec, o_svdec, crout_svdec])
+ comb += self.no_out_vec.eq(~Cat(*l).bool()) # all output scalar
+
+ # condition registers (CR)
+ for to_reg, cr, name, svdec in (
+ (e.read_cr1, self.dec_cr_in, "cr_bitfield", crin_svdec),
+ (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", crin_svdec_b),
+ (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", crin_svdec_o),
+ (e.write_cr, self.dec_cr_out, "cr_bitfield", crout_svdec)):
+ fromreg = getattr(cr, name)
+ comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
+ comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
+ comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
+ with m.If(svdec.isvec):
+ # check if this is CR0 or CR1: treated differently
+ # (does not "listen" to EXTRA2/3 spec for a start)
+ # also: the CRs start from completely different locations
+ with m.If(cr.sv_override == 1): # CR0
+ offs = SVP64CROffs.CR0
+ comb += to_reg.data.eq(srcstep+offs)
+ with m.Elif(cr.sv_override == 2): # CR1
+ offs = SVP64CROffs.CR1
+ comb += to_reg.data.eq(srcstep+1)
+ with m.Else():
+ comb += to_reg.data.eq(srcstep+svdec.cr_out) # 7-bit out
+ with m.Else():
+ comb += to_reg.data.eq(svdec.cr_out) # 7-bit output
+ comb += to_reg.ok.eq(fromreg.ok)
+
+ else:
+ # connect up to/from read/write GPRs
+ for to_reg, fromreg in ((e.read_reg1, dec_a.reg_out),
+ (e.read_reg2, dec_b.reg_out),
+ (e.read_reg3, dec_c.reg_out),
+ (e.write_reg, dec_o.reg_out),
+ (e.write_ea, dec_o2.reg_out)):
+ comb += to_reg.data.eq(fromreg.data)
+ comb += to_reg.ok.eq(fromreg.ok)
+
+ # connect up to/from read/write CRs
+ for to_reg, cr, name in (
+ (e.read_cr1, self.dec_cr_in, "cr_bitfield", ),
+ (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", ),
+ (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", ),
+ (e.write_cr, self.dec_cr_out, "cr_bitfield", )):
+ fromreg = getattr(cr, name)
+ comb += to_reg.data.eq(fromreg.data)
+ comb += to_reg.ok.eq(fromreg.ok)
# SPRs out
comb += e.read_spr1.eq(dec_a.spr_out)
comb += e.write_fast1.eq(dec_o.fast_out)
comb += e.write_fast2.eq(dec_o2.fast_out)
- # condition registers (CR)
- comb += e.read_cr1.eq(self.dec_cr_in.cr_bitfield)
- comb += e.read_cr2.eq(self.dec_cr_in.cr_bitfield_b)
- comb += e.read_cr3.eq(self.dec_cr_in.cr_bitfield_o)
- comb += e.write_cr.eq(self.dec_cr_out.cr_bitfield)
-
# sigh this is exactly the sort of thing for which the
# decoder is designed to not need. MTSPR, MFSPR and others need
# access to the XER bits. however setting e.oe is not appropriate
comb += self.do_copy("cia", self.state.pc, True) # copy of PC "state"
+
def get_rdflags(e, cu):
rdl = []
for idx in range(cu.n_src):
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