return m
-class SVP64RegExtra(Elaboratable):
- """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
-
- incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
- depending on info in one of the positions in the EXTRA field.
+class SVP64ExtraSpec(Elaboratable):
+ """SVP64ExtraSpec - decodes SVP64 Extra specification.
- designed so that "no change" to the 5-bit register number occurs if
- SV either does not apply or the relevant EXTRA2/3 field bits are zero.
+ selects the required EXTRA2/3 field.
see https://libre-soc.org/openpower/sv/svp64/
"""
self.extra = Signal(10, reset_less=True)
self.etype = Signal(SVEtype, reset_less=True) # 2 or 3 bits
self.idx = Signal(SVEXTRA, reset_less=True) # which part of extra
- self.reg_in = Signal(5) # incoming reg number (5 bits, RA, RB)
- self.reg_out = Signal(7) # extra-augmented output (7 bits)
- self.isvec = Signal(1) # reg is marked as vector if true
+ self.spec = Signal(3) # EXTRA spec for the register
def elaborate(self, platform):
m = Module()
comb = m.d.comb
-
- # first get the spec. if not changed it's "scalar identity behaviour"
- # which is zero which is ok.
- spec = Signal(3)
+ spec = self.spec
# back in the LDSTRM-* and RM-* files generated by sv_analysis.py
# we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
# which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
- # the register-extension information. extract those how
+ # the register-extension information. extract those now
with m.Switch(self.etype):
# 2-bit index selection mode
with m.Case(SVEtype.EXTRA2):
comb += spec.eq(self.extra[6:9])
# cannot fit more than 9 bits so there is no 4th thing
+ return m
+
+
+class SVP64RegExtra(SVP64ExtraSpec):
+ """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
+
+ incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
+ depending on info in one of the positions in the EXTRA field.
+
+ designed so that "no change" to the 5-bit register number occurs if
+ SV either does not apply or the relevant EXTRA2/3 field bits are zero.
+
+ see https://libre-soc.org/openpower/sv/svp64/
+ """
+ def __init__(self):
+ SVP64ExtraSpec.__init__(self)
+ self.reg_in = Signal(5) # incoming reg number (5 bits, RA, RB)
+ self.reg_out = Signal(7) # extra-augmented output (7 bits)
+ self.isvec = Signal(1) # reg is marked as vector if true
+
+ def elaborate(self, platform):
+ m = super().elaborate(platform) # select required EXTRA2/3
+ comb = m.d.comb
+
+ # first get the spec. if not changed it's "scalar identity behaviour"
+ # which is zero which is ok.
+ spec = self.spec
+
# now decode it. bit 2 is "scalar/vector". note that spec could be zero
# from above, which (by design) has the effect of "no change", below.
return m
+class SVP64CRExtra(SVP64ExtraSpec):
+ """SVP64CRExtra - decodes SVP64 Extra fields to determine CR extension
+
+ incoming 3-bit CR is turned into a 7-bit and marked as scalar/vector
+ depending on info in one of the positions in the EXTRA field.
+
+ yes, really, 128 CRs. INT is 128, FP is 128, therefore CRs are 128.
+
+ designed so that "no change" to the 3-bit CR register number occurs if
+ SV either does not apply or the relevant EXTRA2/3 field bits are zero.
+
+ see https://libre-soc.org/openpower/sv/svp64/appendix
+ """
+ def __init__(self):
+ SVP64ExtraSpec.__init__(self)
+ self.cr_in = Signal(3) # incoming CR number (3 bits, BA[2:5], BFA)
+ self.cr_out = Signal(7) # extra-augmented CR output (7 bits)
+ self.isvec = Signal(1) # reg is marked as vector if true
+
+ def elaborate(self, platform):
+ m = super().elaborate(platform) # select required EXTRA2/3
+ comb = m.d.comb
+
+ # first get the spec. if not changed it's "scalar identity behaviour"
+ # which is zero which is ok.
+ spec = self.spec
+
+ # now decode it. bit 2 is "scalar/vector". note that spec could be zero
+ # from above, which (by design) has the effect of "no change", below.
+
+ # simple: isvec is top bit of spec
+ comb += self.isvec.eq(spec[2])
+
+ # decode vector differently from scalar, insert bits 0 and 1 accordingly
+ with m.If(self.isvec):
+ # Vector: shifted up, extra in LSBs (CR << 4) | (spec[0:1] << 2)
+ comb += self.cr_out.eq(Cat(Const(0, 2), spec[:2], self.cr_in))
+ with m.Else():
+ # Scalar: not shifted up, extra in MSBs CR | (spec[0:1] << 3)
+ comb += self.cr_out.eq(Cat(self.cr_in, spec[:2]))
+
+ return m
+
+
class DecodeA(Elaboratable):
"""DecodeA from instruction
def __init__(self, dec):
self.dec = dec
- self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(In1Sel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(7, name="reg_a")
- self.reg_isvec = Signal(1, name="reg_a_isvec") # TODO: in reg_out
+ self.reg_out = Data(5, name="reg_a")
self.spr_out = Data(SPR, "spr_a")
self.fast_out = Data(3, "fast_a")
m = Module()
comb = m.d.comb
op = self.dec.op
+ reg = self.reg_out
m.submodules.sprmap = sprmap = SPRMap()
- m.submodules.svdec = svdec = SVP64RegExtra()
-
- # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
- reg = Signal(5, reset_less=True)
# select Register A field
ra = Signal(5, reset_less=True)
with m.If((self.sel_in == In1Sel.RA) |
((self.sel_in == In1Sel.RA_OR_ZERO) &
(ra != Const(0, 5)))):
- comb += reg.eq(ra)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(ra)
+ comb += reg.ok.eq(1)
# some Logic/ALU ops have RS as the 3rd arg, but no "RA".
# moved it to 1st position (in1_sel)... because
rs = Signal(5, reset_less=True)
comb += rs.eq(self.dec.RS)
with m.If(self.sel_in == In1Sel.RS):
- comb += reg.eq(rs)
- comb += self.reg_out.ok.eq(1)
-
- # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
- # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
- # which in turn were auto-generated by sv_analysis.py
-
- extra = self.sv_rm.extra # SVP64 extra bits 10:18
- comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
- comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
- comb += svdec.idx.eq(op.sv_in1) # SVP64 reg #1 (matches in1_sel)
- comb += svdec.reg_in.eq(reg) # 5-bit (RA, RS)
-
- # outputs: 7-bit reg number and whether it's vectorised
- comb += self.reg_out.data.eq(svdec.reg_out)
- comb += self.reg_isvec.eq(svdec.isvec)
+ comb += reg.data.eq(rs)
+ comb += reg.ok.eq(1)
# decode Fast-SPR based on instruction type
with m.Switch(op.internal_op):
def __init__(self, dec):
self.dec = dec
- self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(In2Sel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(5, "reg_b")
+ self.reg_out = Data(7, "reg_b")
+ self.reg_isvec = Signal(1, name="reg_b_isvec") # TODO: in reg_out
self.fast_out = Data(3, "fast_b")
def elaborate(self, platform):
m = Module()
comb = m.d.comb
+ op = self.dec.op
+ reg = self.reg_out
# select Register B field
with m.Switch(self.sel_in):
with m.Case(In2Sel.RB):
- comb += self.reg_out.data.eq(self.dec.RB)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RB)
+ comb += reg.ok.eq(1)
with m.Case(In2Sel.RS):
# for M-Form shiftrot
- comb += self.reg_out.data.eq(self.dec.RS)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RS)
+ comb += reg.ok.eq(1)
# decode SPR2 based on instruction type
- op = self.dec.op
# BCREG implicitly uses LR or TAR for 2nd reg
# CTR however is already in fast_spr1 *not* 2.
with m.If(op.internal_op == MicrOp.OP_BCREG):
def __init__(self, dec):
self.dec = dec
- self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(In3Sel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
self.reg_out = Data(5, "reg_c")
def elaborate(self, platform):
m = Module()
comb = m.d.comb
+ op = self.dec.op
+ reg = self.reg_out
# select Register C field
with m.Switch(self.sel_in):
with m.Case(In3Sel.RB):
# for M-Form shiftrot
- comb += self.reg_out.data.eq(self.dec.RB)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RB)
+ comb += reg.ok.eq(1)
with m.Case(In3Sel.RS):
- comb += self.reg_out.data.eq(self.dec.RS)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RS)
+ comb += reg.ok.eq(1)
return m
def __init__(self, dec):
self.dec = dec
- self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(OutSel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
self.reg_out = Data(5, "reg_o")
comb = m.d.comb
m.submodules.sprmap = sprmap = SPRMap()
op = self.dec.op
+ reg = self.reg_out
# select Register out field
with m.Switch(self.sel_in):
with m.Case(OutSel.RT):
- comb += self.reg_out.data.eq(self.dec.RT)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RT)
+ comb += reg.ok.eq(1)
with m.Case(OutSel.RA):
- comb += self.reg_out.data.eq(self.dec.RA)
- comb += self.reg_out.ok.eq(1)
+ comb += reg.data.eq(self.dec.RA)
+ comb += reg.ok.eq(1)
with m.Case(OutSel.SPR):
spr = Signal(10, reset_less=True)
comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
comb += self.spr_out.eq(sprmap.spr_o)
comb += self.fast_out.eq(sprmap.fast_o)
+ # determine Fast Reg
with m.Switch(op.internal_op):
# BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
class DecodeOut2(Elaboratable):
"""DecodeOut2 from instruction
- decodes output registers
+ decodes output registers (2nd one). note that RA is *implicit* below,
+ which now causes problems with SVP64
+
+ TODO: SVP64 is a little more complex, here. svp64 allows extending
+ by one more destination by having one more EXTRA field. RA-as-src
+ is not the same as RA-as-dest. limited in that it's the same first
+ 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
+ for operations that have src-as-dest: mostly this is LD/ST-with-update
+ but there are others.
"""
def __init__(self, dec):
self.dec = dec
- self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(OutSel, reset_less=True)
self.lk = Signal(reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(5, "reg_o")
- self.fast_out = Data(3, "fast_o")
+ self.reg_out = Data(5, "reg_o2")
+ self.fast_out = Data(3, "fast_o2")
def elaborate(self, platform):
m = Module()
comb = m.d.comb
+ op = self.dec.op
+ #m.submodules.svdec = svdec = SVP64RegExtra()
+
+ # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
+ #reg = Signal(5, reset_less=True)
if hasattr(self.dec.op, "upd"):
# update mode LD/ST uses read-reg A also as an output
with m.If(self.dec.op.upd == LDSTMode.update):
- comb += self.reg_out.eq(self.dec.RA)
+ comb += self.reg_out.data.eq(self.dec.RA)
comb += self.reg_out.ok.eq(1)
# B, BC or BCREG: potential implicit register (LR) output
# these give bl, bcl, bclrl, etc.
- op = self.dec.op
with m.Switch(op.internal_op):
# BC* implicit register (LR)
def __init__(self, dec):
self.dec = dec
- self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(CRInSel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
self.cr_bitfield = Data(3, "cr_bitfield")
def elaborate(self, platform):
m = Module()
- m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
- reverse_o=True)
-
comb = m.d.comb
op = self.dec.op
+ m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
+ reverse_o=True)
+ # zero-initialisation
comb += self.cr_bitfield.ok.eq(0)
comb += self.cr_bitfield_b.ok.eq(0)
+ comb += self.cr_bitfield_o.ok.eq(0)
comb += self.whole_reg.ok.eq(0)
+
+ # select the relevant CR bitfields
with m.Switch(self.sel_in):
with m.Case(CRInSel.NONE):
pass # No bitfield activated
def __init__(self, dec):
self.dec = dec
- self.sv_rm = SVP64Rec() # SVP64 RM field
self.rc_in = Signal(reset_less=True)
self.sel_in = Signal(CROutSel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
comb += self.cr_bitfield.ok.eq(0)
comb += self.whole_reg.ok.eq(0)
+
with m.Switch(self.sel_in):
with m.Case(CROutSel.NONE):
pass # No bitfield activated
self.state = state
def get_col_subset(self, do):
- subset = {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
+ subset = { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
for k, v in record_names.items():
if hasattr(do, k):
subset.add(v)
comb += dec_rc.sel_in.eq(op.rc_sel)
comb += dec_oe.sel_in.eq(op.rc_sel) # XXX should be OE sel
comb += self.dec_cr_in.sel_in.eq(op.cr_in)
- comb += self.dec_cr_in.sv_rm.eq(self.sv_rm)
- comb += self.dec_cr_out.sv_rm.eq(self.sv_rm)
comb += self.dec_cr_out.sel_in.eq(op.cr_out)
comb += self.dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
super().__init__(dec, opkls, fn_name, final, state)
self.exc = LDSTException("dec2_exc")
+ self.cr_out_isvec = Signal(1, name="cr_out_isvec")
+ self.cr_in_isvec = Signal(1, name="cr_in_isvec")
+ self.cr_in_b_isvec = Signal(1, name="cr_in_b_isvec")
+ self.cr_in_o_isvec = Signal(1, name="cr_in_o_isvec")
+ self.in1_isvec = Signal(1, name="reg_a_isvec")
+ self.in2_isvec = Signal(1, name="reg_b_isvec")
+ self.in3_isvec = Signal(1, name="reg_c_isvec")
+ self.o_isvec = Signal(1, name="reg_o_isvec")
+ self.o2_isvec = Signal(1, name="reg_o2_isvec")
+
def get_col_subset(self, opkls):
subset = super().get_col_subset(opkls)
subset.add("asmcode")
subset.add("sv_in2")
subset.add("sv_in3")
subset.add("sv_out")
+ subset.add("sv_cr_in")
+ subset.add("sv_cr_out")
subset.add("SV_Etype")
subset.add("SV_Ptype")
subset.add("lk")
m.submodules.dec_o = dec_o = DecodeOut(self.dec)
m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
+ # and SVP64 Extra decoders
+ m.submodules.crout_svdec = crout_svdec = SVP64CRExtra()
+ m.submodules.crin_svdec = crin_svdec = SVP64CRExtra()
+ m.submodules.crin_svdec_b = crin_svdec_b = SVP64CRExtra()
+ m.submodules.crin_svdec_o = crin_svdec_o = SVP64CRExtra()
+ m.submodules.in1_svdec = in1_svdec = SVP64RegExtra()
+ m.submodules.in2_svdec = in2_svdec = SVP64RegExtra()
+ m.submodules.in3_svdec = in3_svdec = SVP64RegExtra()
+ m.submodules.o_svdec = o_svdec = SVP64RegExtra()
+ m.submodules.o2_svdec = o2_svdec = SVP64RegExtra()
+
+ # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
+ reg = Signal(5, reset_less=True)
+
# copy instruction through...
for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]:
comb += i.eq(self.dec.opcode_in)
- # ... and svp64 rm
- for i in [dec_a.insn_in, dec_b.insn_in,
- dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]:
- comb += i.eq(self.sv_rm)
+ # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
+ # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
+ # which in turn were auto-generated by sv_analysis.py
+ extra = self.sv_rm.extra # SVP64 extra bits 10:18
+
+ #######
+ # CR out
+ comb += crout_svdec.idx.eq(op.sv_cr_out) # SVP64 CR out
+ comb += self.cr_out_isvec.eq(crout_svdec.isvec)
+
+ #######
+ # CR in - index selection slightly different due to shared CR field sigh
+ cr_a_idx = Signal(SVEXTRA)
+ cr_b_idx = Signal(SVEXTRA)
+
+ # these change slightly, when decoding BA/BB. really should have
+ # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
+ comb += cr_a_idx.eq(op.sv_cr_in)
+ comb += cr_b_idx.eq(SVEXTRA.NONE)
+ with m.If(op.sv_cr_in == SVEXTRA.Idx_1_2.value):
+ comb += cr_a_idx.eq(SVEXTRA.Idx1)
+ comb += cr_b_idx.eq(SVEXTRA.Idx2)
+
+ comb += self.cr_in_isvec.eq(crin_svdec.isvec)
+ comb += self.cr_in_b_isvec.eq(crin_svdec_b.isvec)
+ comb += self.cr_in_o_isvec.eq(crin_svdec_o.isvec)
+
+ # indices are slightly different, BA/BB mess sorted above
+ comb += crin_svdec.idx.eq(cr_a_idx) # SVP64 CR in A
+ comb += crin_svdec_b.idx.eq(cr_b_idx) # SVP64 CR in B
+ comb += crin_svdec_o.idx.eq(op.sv_cr_out) # SVP64 CR out
# ...and subdecoders' input fields
comb += dec_a.sel_in.eq(op.in1_sel)
comb += dec_o2.lk.eq(do.lk)
# registers a, b, c and out and out2 (LD/ST EA)
- for to_reg, fromreg in (
- (e.read_reg1, dec_a.reg_out),
- (e.read_reg2, dec_b.reg_out),
- (e.read_reg3, dec_c.reg_out),
- (e.write_reg, dec_o.reg_out),
- (e.write_ea, dec_o2.reg_out)):
- comb += to_reg.data.eq(fromreg.data)
+ for to_reg, fromreg, svdec in (
+ (e.read_reg1, dec_a.reg_out, in1_svdec),
+ (e.read_reg2, dec_b.reg_out, in2_svdec),
+ (e.read_reg3, dec_c.reg_out, in3_svdec),
+ (e.write_reg, dec_o.reg_out, o_svdec),
+ (e.write_ea, dec_o2.reg_out, o2_svdec)):
+ comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
+ comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
+ comb += svdec.reg_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
+ comb += to_reg.data.eq(svdec.reg_out) # 7-bit output
comb += to_reg.ok.eq(fromreg.ok)
+ comb += in1_svdec.idx.eq(op.sv_in1) # SVP64 reg #1 (matches in1_sel)
+ comb += in2_svdec.idx.eq(op.sv_in2) # SVP64 reg #2 (matches in2_sel)
+ comb += in3_svdec.idx.eq(op.sv_in3) # SVP64 reg #3 (matches in3_sel)
+ comb += o_svdec.idx.eq(op.sv_out) # SVP64 output (matches out_sel)
+ # XXX TODO - work out where this should come from. the problem is
+ # that LD-with-update is implied (computed from "is instruction in
+ # "update mode" rather than specified cleanly as its own CSV column
+ #comb += o2_svdec.idx.eq(op.sv_out) # SVP64 output (implicit)
+
+ comb += self.in1_isvec.eq(in1_svdec.isvec)
+ comb += self.in2_isvec.eq(in2_svdec.isvec)
+ comb += self.in3_isvec.eq(in3_svdec.isvec)
+ comb += self.o_isvec.eq(o_svdec.isvec)
+ comb += self.o2_isvec.eq(o2_svdec.isvec)
+
# SPRs out
comb += e.read_spr1.eq(dec_a.spr_out)
comb += e.write_spr.eq(dec_o.spr_out)
comb += e.write_fast2.eq(dec_o2.fast_out)
# condition registers (CR)
- comb += e.read_cr1.eq(self.dec_cr_in.cr_bitfield)
- comb += e.read_cr2.eq(self.dec_cr_in.cr_bitfield_b)
- comb += e.read_cr3.eq(self.dec_cr_in.cr_bitfield_o)
- comb += e.write_cr.eq(self.dec_cr_out.cr_bitfield)
+ for to_reg, fromreg, svdec in (
+ (e.read_cr1, self.dec_cr_in.cr_bitfield, crin_svdec),
+ (e.read_cr2, self.dec_cr_in.cr_bitfield_b, crin_svdec_b),
+ (e.read_cr3, self.dec_cr_in.cr_bitfield_o, crin_svdec_o),
+ (e.write_cr, self.dec_cr_out.cr_bitfield, crout_svdec)):
+ comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
+ comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
+ comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
+ comb += to_reg.data.eq(svdec.cr_out) # 7-bit output
+ comb += to_reg.ok.eq(fromreg.ok)
# sigh this is exactly the sort of thing for which the
# decoder is designed to not need. MTSPR, MFSPR and others need
comb += self.do_copy("cia", self.state.pc, True) # copy of PC "state"
+# SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
+# identifies if an instruction is a SVP64-encoded prefix, and extracts
+# the 24-bit SVP64 context (RM) if it is
+class SVP64PowerDecoder(Elaboratable):
+
+ def __init__(self):
+ self.opcode_in = Signal(32, reset_less=True)
+ self.raw_opcode_in = Signal.like(self.opcode_in, reset_less=True)
+ self.is_svp64_mode = Signal(1, reset_less=True)
+ self.svp64_rm = Signal(24, reset_less=True)
+ self.bigendian = Signal(reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ comb = m.d.comb
+ # sigh copied this from TopPowerDecoder
+ # raw opcode in assumed to be in LE order: byte-reverse it to get BE
+ raw_le = self.raw_opcode_in
+ l = []
+ for i in range(0, 32, 8):
+ l.append(raw_le[i:i+8])
+ l.reverse()
+ raw_be = Cat(*l)
+ comb += self.opcode_in.eq(Mux(self.bigendian, raw_be, raw_le))
+
+ # start identifying if the incoming opcode is SVP64 prefix)
+ major = Signal(6, reset_less=True)
+
+ comb += major.eq(self.opcode_in[26:32])
+ comb += self.is_svp64_mode.eq((major == Const(1, 6)) & # EXT01
+ self.opcode_in[31-7] & # identifier
+ self.opcode_in[31-9]) # bits
+
+ # now grab the 24-bit ReMap context bits,
+ rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM
+ l = []
+ for idx in rmfields:
+ l.append(self.opcode_in[32-idx])
+ comb += self.svp64_rm.eq(Cat(*l))
+
+ return m
+
+ def ports(self):
+ return [self.opcode_in, self.raw_opcode_in, self.is_svp64_mode,
+ self.svp64_rm, self.bigendian]
+
def get_rdflags(e, cu):
rdl = []
for idx in range(cu.n_src):
if __name__ == '__main__':
+ svp64 = SVP64PowerDecoder()
+ vl = rtlil.convert(svp64, ports=svp64.ports())
+ with open("svp64_dec.il", "w") as f:
+ f.write(vl)
pdecode = create_pdecode()
dec2 = PowerDecode2(pdecode)
vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
projects / soc.git / blobdiff