pass SPR MicroOp to MMU function unit

[soc.git] / src / soc / decoder / power_decoder2.py

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index a5fab3da3e5b71d0f9e5df3a06d152fbb090a514..bfe9eda4d3a29f6f6f37a3d4248248fcff6d0c90 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -889,7 +889,16 @@ class PowerDecodeSubset(Elaboratable):
 
         # set up instruction type
         # no op: defaults to OP_ILLEGAL
-        comb += self.do_copy("insn_type", self.op_get("internal_op"))
+        if self.fn_name=="MMU":
+            # mmu is special case: needs SPR opcode as well
+            mmu0 = self.mmu0_spr_dec
+            with m.If(((mmu0.dec.op.internal_op == MicrOp.OP_MTSPR) |
+                       (mmu0.dec.op.internal_op == MicrOp.OP_MFSPR))):
+                comb += self.do_copy("insn_type", mmu0.op_get("internal_op"))
+            with m.Else():
+                comb += self.do_copy("insn_type", self.op_get("internal_op"))
+        else:
+            comb += self.do_copy("insn_type", self.op_get("internal_op"))
 
         # function unit for decoded instruction: requires minor redirect
         # for SPR set/get
@@ -1307,7 +1316,8 @@ class SVP64PowerDecoder(Elaboratable):
         l = []
         for idx in rmfields:
             l.append(self.opcode_in[32-idx])
-        comb += self.svp64_rm.eq(Cat(*l))
+        with m.If(self.is_svp64_mode):
+            comb += self.svp64_rm.eq(Cat(*l))
 
         return m