return m
-class SVP64RegExtra(Elaboratable):
- """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
+class SVP64ExtraSpec(Elaboratable):
+ """SVP64ExtraSpec - decodes SVP64 Extra specification.
- incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
- depending on info in one of the positions in the EXTRA field.
-
- designed so that "no change" to the 5-bit register number occurs if
- SV either does not apply or the relevant EXTRA2/3 field bits are zero.
+ selects the required EXTRA2/3 field.
see https://libre-soc.org/openpower/sv/svp64/
"""
self.extra = Signal(10, reset_less=True)
self.etype = Signal(SVEtype, reset_less=True) # 2 or 3 bits
self.idx = Signal(SVEXTRA, reset_less=True) # which part of extra
- self.reg_in = Signal(5) # incoming reg number (5 bits, RA, RB)
- self.reg_out = Signal(7) # extra-augmented output (7 bits)
- self.isvec = Signal(1) # reg is marked as vector if true
+ self.spec = Signal(3) # EXTRA spec for the register
def elaborate(self, platform):
m = Module()
comb = m.d.comb
-
- # first get the spec. if not changed it's "scalar identity behaviour"
- # which is zero which is ok.
- spec = Signal(3)
+ spec = self.spec
# back in the LDSTRM-* and RM-* files generated by sv_analysis.py
# we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
comb += spec.eq(self.extra[6:9])
# cannot fit more than 9 bits so there is no 4th thing
+ return m
+
+
+class SVP64RegExtra(SVP64ExtraSpec):
+ """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
+
+ incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
+ depending on info in one of the positions in the EXTRA field.
+
+ designed so that "no change" to the 5-bit register number occurs if
+ SV either does not apply or the relevant EXTRA2/3 field bits are zero.
+
+ see https://libre-soc.org/openpower/sv/svp64/
+ """
+ def __init__(self):
+ SVP64ExtraSpec.__init__(self)
+ self.reg_in = Signal(5) # incoming reg number (5 bits, RA, RB)
+ self.reg_out = Signal(7) # extra-augmented output (7 bits)
+ self.isvec = Signal(1) # reg is marked as vector if true
+
+ def elaborate(self, platform):
+ m = super().elaborate(platform) # select required EXTRA2/3
+ comb = m.d.comb
+
+ # first get the spec. if not changed it's "scalar identity behaviour"
+ # which is zero which is ok.
+ spec = self.spec
+
# now decode it. bit 2 is "scalar/vector". note that spec could be zero
# from above, which (by design) has the effect of "no change", below.
return m
+class SVP64CRExtra(SVP64ExtraSpec):
+ """SVP64CRExtra - decodes SVP64 Extra fields to determine CR extension
+
+ incoming 3-bit CR is turned into a 7-bit and marked as scalar/vector
+ depending on info in one of the positions in the EXTRA field.
+
+ yes, really, 128 CRs. INT is 128, FP is 128, therefore CRs are 128.
+
+ designed so that "no change" to the 3-bit CR register number occurs if
+ SV either does not apply or the relevant EXTRA2/3 field bits are zero.
+
+ see https://libre-soc.org/openpower/sv/svp64/appendix
+ """
+ def __init__(self):
+ SVP64ExtraSpec.__init__(self)
+ self.cr_in = Signal(3) # incoming CR number (3 bits, BA[2:5], BFA)
+ self.cr_out = Signal(7) # extra-augmented CR output (7 bits)
+ self.isvec = Signal(1) # reg is marked as vector if true
+
+ def elaborate(self, platform):
+ m = super().elaborate(platform) # select required EXTRA2/3
+ comb = m.d.comb
+
+ # first get the spec. if not changed it's "scalar identity behaviour"
+ # which is zero which is ok.
+ spec = self.spec
+
+ # now decode it. bit 2 is "scalar/vector". note that spec could be zero
+ # from above, which (by design) has the effect of "no change", below.
+
+ # simple: isvec is top bit of spec
+ comb += self.isvec.eq(spec[2])
+
+ # decode vector differently from scalar, insert bits 0 and 1 accordingly
+ with m.If(self.isvec):
+ # Vector: shifted up, extra in LSBs (CR << 4) | (spec[0:1] << 2)
+ comb += self.cr_out.eq(Cat(Const(0, 2), spec[:2], self.cr_in))
+ with m.Else():
+ # Scalar: not shifted up, extra in MSBs CR | (spec[0:1] << 3)
+ comb += self.cr_out.eq(Cat(self.cr_in, spec[:2]))
+
+ return m
+
+
class DecodeA(Elaboratable):
"""DecodeA from instruction
self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(In2Sel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(5, "reg_b")
+ self.reg_out = Data(7, "reg_b")
self.reg_isvec = Signal(1, name="reg_b_isvec") # TODO: in reg_out
self.fast_out = Data(3, "fast_b")
self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(In3Sel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(5, "reg_c")
+ self.reg_out = Data(7, "reg_c")
self.reg_isvec = Signal(1, name="reg_c_isvec") # TODO: in reg_out
def elaborate(self, platform):
self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(OutSel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(5, "reg_o")
- self.reg_isvec = Signal(1, name="reg_c_isvec") # TODO: in reg_out
+ self.reg_out = Data(7, "reg_o")
+ self.reg_isvec = Signal(1, name="reg_o_isvec") # TODO: in reg_out
self.spr_out = Data(SPR, "spr_o")
self.fast_out = Data(3, "fast_o")
class DecodeOut2(Elaboratable):
"""DecodeOut2 from instruction
- decodes output registers.
+ decodes output registers (2nd one). note that RA is *implicit* below,
+ which now causes problems with SVP64
TODO: SVP64 is a little more complex, here. svp64 allows extending
by one more destination by having one more EXTRA field. RA-as-src
self.sel_in = Signal(OutSel, reset_less=True)
self.lk = Signal(reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(5, "reg_o")
- self.fast_out = Data(3, "fast_o")
+ self.reg_out = Data(7, "reg_o2")
+ #self.reg_isvec = Signal(1, name="reg_o2_isvec") # TODO: in reg_out
+ self.fast_out = Data(3, "fast_o2")
def elaborate(self, platform):
m = Module()
comb = m.d.comb
+ op = self.dec.op
+ #m.submodules.svdec = svdec = SVP64RegExtra()
+
+ # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
+ #reg = Signal(5, reset_less=True)
if hasattr(self.dec.op, "upd"):
# update mode LD/ST uses read-reg A also as an output
with m.If(self.dec.op.upd == LDSTMode.update):
- comb += self.reg_out.eq(self.dec.RA)
+ comb += self.reg_out.data.eq(self.dec.RA)
comb += self.reg_out.ok.eq(1)
# B, BC or BCREG: potential implicit register (LR) output
# these give bl, bcl, bclrl, etc.
- op = self.dec.op
with m.Switch(op.internal_op):
# BC* implicit register (LR)
comb += self.cr_bitfield.ok.eq(0)
comb += self.cr_bitfield_b.ok.eq(0)
+ comb += self.cr_bitfield_o.ok.eq(0)
comb += self.whole_reg.ok.eq(0)
+
with m.Switch(self.sel_in):
with m.Case(CRInSel.NONE):
pass # No bitfield activated
projects / soc.git / blobdiff