return m
-class SVP64RegExtra(Elaboratable):
- """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
+class SVP64ExtraSpec(Elaboratable):
+ """SVP64ExtraSpec - decodes SVP64 Extra specification.
- incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
- depending on info in one of the positions in the EXTRA field.
-
- designed so that "no change" to the 5-bit register number occurs if
- SV either does not apply or the relevant EXTRA2/3 field bits are zero.
+ selects the required EXTRA2/3 field.
see https://libre-soc.org/openpower/sv/svp64/
"""
self.extra = Signal(10, reset_less=True)
self.etype = Signal(SVEtype, reset_less=True) # 2 or 3 bits
self.idx = Signal(SVEXTRA, reset_less=True) # which part of extra
- self.reg_in = Signal(5) # incoming reg number (5 bits, RA, RB)
- self.reg_out = Signal(7) # extra-augmented output (7 bits)
- self.isvec = Signal(1) # reg is marked as vector if true
+ self.spec = Signal(3) # EXTRA spec for the register
def elaborate(self, platform):
m = Module()
comb = m.d.comb
-
- # first get the spec. if not changed it's "scalar identity behaviour"
- # which is zero which is ok.
- spec = Signal(3)
+ spec = self.spec
# back in the LDSTRM-* and RM-* files generated by sv_analysis.py
# we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
# which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
- # the register-extension information. extract those how
+ # the register-extension information. extract those now
with m.Switch(self.etype):
# 2-bit index selection mode
with m.Case(SVEtype.EXTRA2):
comb += spec.eq(self.extra[6:9])
# cannot fit more than 9 bits so there is no 4th thing
+ return m
+
+
+class SVP64RegExtra(SVP64ExtraSpec):
+ """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
+
+ incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
+ depending on info in one of the positions in the EXTRA field.
+
+ designed so that "no change" to the 5-bit register number occurs if
+ SV either does not apply or the relevant EXTRA2/3 field bits are zero.
+
+ see https://libre-soc.org/openpower/sv/svp64/
+ """
+ def __init__(self):
+ SVP64ExtraSpec.__init__(self)
+ self.reg_in = Signal(5) # incoming reg number (5 bits, RA, RB)
+ self.reg_out = Signal(7) # extra-augmented output (7 bits)
+ self.isvec = Signal(1) # reg is marked as vector if true
+
+ def elaborate(self, platform):
+ m = super().elaborate(platform) # select required EXTRA2/3
+ comb = m.d.comb
+
+ # first get the spec. if not changed it's "scalar identity behaviour"
+ # which is zero which is ok.
+ spec = self.spec
+
# now decode it. bit 2 is "scalar/vector". note that spec could be zero
# from above, which (by design) has the effect of "no change", below.
return m
+class SVP64CRExtra(SVP64ExtraSpec):
+ """SVP64CRExtra - decodes SVP64 Extra fields to determine CR extension
+
+ incoming 3-bit CR is turned into a 7-bit and marked as scalar/vector
+ depending on info in one of the positions in the EXTRA field.
+
+ yes, really, 128 CRs. INT is 128, FP is 128, therefore CRs are 128.
+
+ designed so that "no change" to the 3-bit CR register number occurs if
+ SV either does not apply or the relevant EXTRA2/3 field bits are zero.
+
+ see https://libre-soc.org/openpower/sv/svp64/appendix
+ """
+ def __init__(self):
+ SVP64ExtraSpec.__init__(self)
+ self.cr_in = Signal(3) # incoming CR number (3 bits, BA[2:5], BFA)
+ self.cr_out = Signal(7) # extra-augmented CR output (7 bits)
+ self.isvec = Signal(1) # reg is marked as vector if true
+
+ def elaborate(self, platform):
+ m = super().elaborate(platform) # select required EXTRA2/3
+ comb = m.d.comb
+
+ # first get the spec. if not changed it's "scalar identity behaviour"
+ # which is zero which is ok.
+ spec = self.spec
+
+ # now decode it. bit 2 is "scalar/vector". note that spec could be zero
+ # from above, which (by design) has the effect of "no change", below.
+
+ # simple: isvec is top bit of spec
+ comb += self.isvec.eq(spec[2])
+
+ # decode vector differently from scalar, insert bits 0 and 1 accordingly
+ with m.If(self.isvec):
+ # Vector: shifted up, extra in LSBs (CR << 4) | (spec[0:1] << 2)
+ comb += self.cr_out.eq(Cat(Const(0, 2), spec[:2], self.cr_in))
+ with m.Else():
+ # Scalar: not shifted up, extra in MSBs CR | (spec[0:1] << 3)
+ comb += self.cr_out.eq(Cat(self.cr_in, spec[:2]))
+
+ return m
+
+
class DecodeA(Elaboratable):
"""DecodeA from instruction
self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(In2Sel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(5, "reg_b")
+ self.reg_out = Data(7, "reg_b")
+ self.reg_isvec = Signal(1, name="reg_b_isvec") # TODO: in reg_out
self.fast_out = Data(3, "fast_b")
def elaborate(self, platform):
m = Module()
comb = m.d.comb
+ op = self.dec.op
+ m.submodules.svdec = svdec = SVP64RegExtra()
+
+ # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
+ reg = Signal(5, reset_less=True)
# select Register B field
with m.Switch(self.sel_in):
with m.Case(In2Sel.RB):
- comb += self.reg_out.data.eq(self.dec.RB)
+ comb += reg.eq(self.dec.RB)
comb += self.reg_out.ok.eq(1)
with m.Case(In2Sel.RS):
# for M-Form shiftrot
- comb += self.reg_out.data.eq(self.dec.RS)
+ comb += reg.eq(self.dec.RS)
comb += self.reg_out.ok.eq(1)
+ # now do the SVP64 munging. different from DecodeA only by sv_in2
+
+ extra = self.sv_rm.extra # SVP64 extra bits 10:18
+ comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
+ comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
+ comb += svdec.idx.eq(op.sv_in2) # SVP64 reg #2 (matches in2_sel)
+ comb += svdec.reg_in.eq(reg) # 5-bit (RA, RS)
+
+ # outputs: 7-bit reg number and whether it's vectorised
+ comb += self.reg_out.data.eq(svdec.reg_out)
+ comb += self.reg_isvec.eq(svdec.isvec)
+
# decode SPR2 based on instruction type
- op = self.dec.op
# BCREG implicitly uses LR or TAR for 2nd reg
# CTR however is already in fast_spr1 *not* 2.
with m.If(op.internal_op == MicrOp.OP_BCREG):
self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(In3Sel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(5, "reg_c")
+ self.reg_out = Data(7, "reg_c")
+ self.reg_isvec = Signal(1, name="reg_c_isvec") # TODO: in reg_out
def elaborate(self, platform):
m = Module()
comb = m.d.comb
+ op = self.dec.op
+ m.submodules.svdec = svdec = SVP64RegExtra()
+
+ # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
+ reg = Signal(5, reset_less=True)
# select Register C field
with m.Switch(self.sel_in):
with m.Case(In3Sel.RB):
# for M-Form shiftrot
- comb += self.reg_out.data.eq(self.dec.RB)
+ comb += reg.eq(self.dec.RB)
comb += self.reg_out.ok.eq(1)
with m.Case(In3Sel.RS):
- comb += self.reg_out.data.eq(self.dec.RS)
+ comb += reg.eq(self.dec.RS)
comb += self.reg_out.ok.eq(1)
+ # now do the SVP64 munging. different from DecodeA only by sv_in3
+
+ extra = self.sv_rm.extra # SVP64 extra bits 10:18
+ comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
+ comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
+ comb += svdec.idx.eq(op.sv_in3) # SVP64 reg #3 (matches in3_sel)
+ comb += svdec.reg_in.eq(reg) # 5-bit (RA, RS)
+
+ # outputs: 7-bit reg number and whether it's vectorised
+ comb += self.reg_out.data.eq(svdec.reg_out)
+ comb += self.reg_isvec.eq(svdec.isvec)
+
return m
self.sv_rm = SVP64Rec() # SVP64 RM field
self.sel_in = Signal(OutSel, reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(5, "reg_o")
+ self.reg_out = Data(7, "reg_o")
+ self.reg_isvec = Signal(1, name="reg_o_isvec") # TODO: in reg_out
self.spr_out = Data(SPR, "spr_o")
self.fast_out = Data(3, "fast_o")
comb = m.d.comb
m.submodules.sprmap = sprmap = SPRMap()
op = self.dec.op
+ m.submodules.svdec = svdec = SVP64RegExtra()
+
+ # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
+ reg = Signal(5, reset_less=True)
# select Register out field
with m.Switch(self.sel_in):
with m.Case(OutSel.RT):
- comb += self.reg_out.data.eq(self.dec.RT)
+ comb += reg.eq(self.dec.RT)
comb += self.reg_out.ok.eq(1)
with m.Case(OutSel.RA):
- comb += self.reg_out.data.eq(self.dec.RA)
+ comb += reg.eq(self.dec.RA)
comb += self.reg_out.ok.eq(1)
with m.Case(OutSel.SPR):
spr = Signal(10, reset_less=True)
comb += self.spr_out.eq(sprmap.spr_o)
comb += self.fast_out.eq(sprmap.fast_o)
+ # now do the SVP64 munging. different from DecodeA only by sv_out
+
+ extra = self.sv_rm.extra # SVP64 extra bits 10:18
+ comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
+ comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
+ comb += svdec.idx.eq(op.sv_out) # SVP64 reg out1 (matches out_sel)
+ comb += svdec.reg_in.eq(reg) # 5-bit (RA, RS)
+
+ # outputs: 7-bit reg number and whether it's vectorised
+ comb += self.reg_out.data.eq(svdec.reg_out)
+ comb += self.reg_isvec.eq(svdec.isvec)
+
+ # determine Fast Reg
with m.Switch(op.internal_op):
# BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
class DecodeOut2(Elaboratable):
"""DecodeOut2 from instruction
- decodes output registers
+ decodes output registers (2nd one). note that RA is *implicit* below,
+ which now causes problems with SVP64
+
+ TODO: SVP64 is a little more complex, here. svp64 allows extending
+ by one more destination by having one more EXTRA field. RA-as-src
+ is not the same as RA-as-dest. limited in that it's the same first
+ 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
+ for operations that have src-as-dest: mostly this is LD/ST-with-update
+ but there are others.
"""
def __init__(self, dec):
self.sel_in = Signal(OutSel, reset_less=True)
self.lk = Signal(reset_less=True)
self.insn_in = Signal(32, reset_less=True)
- self.reg_out = Data(5, "reg_o")
- self.fast_out = Data(3, "fast_o")
+ self.reg_out = Data(7, "reg_o2")
+ #self.reg_isvec = Signal(1, name="reg_o2_isvec") # TODO: in reg_out
+ self.fast_out = Data(3, "fast_o2")
def elaborate(self, platform):
m = Module()
comb = m.d.comb
+ op = self.dec.op
+ #m.submodules.svdec = svdec = SVP64RegExtra()
+
+ # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
+ #reg = Signal(5, reset_less=True)
if hasattr(self.dec.op, "upd"):
# update mode LD/ST uses read-reg A also as an output
with m.If(self.dec.op.upd == LDSTMode.update):
- comb += self.reg_out.eq(self.dec.RA)
+ comb += self.reg_out.data.eq(self.dec.RA)
comb += self.reg_out.ok.eq(1)
# B, BC or BCREG: potential implicit register (LR) output
# these give bl, bcl, bclrl, etc.
- op = self.dec.op
with m.Switch(op.internal_op):
# BC* implicit register (LR)
self.cr_bitfield = Data(3, "cr_bitfield")
self.cr_bitfield_b = Data(3, "cr_bitfield_b")
self.cr_bitfield_o = Data(3, "cr_bitfield_o")
+ self.cr_isvec = Signal(1, name="cr_isvec")
+ self.cr_b_isvec = Signal(1, name="cr_b_isvec")
+ self.cr_o_isvec = Signal(1, name="cr_o_isvec")
self.whole_reg = Data(8, "cr_fxm")
def elaborate(self, platform):
m = Module()
+ comb = m.d.comb
+ op = self.dec.op
+ m.submodules.svdec = svdec = SVP64CRExtra()
+ m.submodules.svdec_b = svdec_b = SVP64CRExtra()
+ m.submodules.svdec_o = svdec_o = SVP64CRExtra()
m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
reverse_o=True)
- comb = m.d.comb
- op = self.dec.op
+ # get the 3-bit reg data before svp64-munging it into 7-bit plus isvec
+ cr_bf = Signal(3, reset_less=True)
+ cr_bf_b = Signal(3, reset_less=True)
+ cr_bf_o = Signal(3, reset_less=True)
+
+ # index selection slightly different due to shared CR field sigh
+ cr_a_idx = Signal(SVEXTRA)
+ cr_b_idx = Signal(SVEXTRA)
+
+ # zero-initialisation
comb += self.cr_bitfield.ok.eq(0)
comb += self.cr_bitfield_b.ok.eq(0)
+ comb += self.cr_bitfield_o.ok.eq(0)
comb += self.whole_reg.ok.eq(0)
+
+ # these change slighly, when decoding BA/BB. really should have
+ # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
+ comb += cr_a_idx.eq(op.sv_cr_in)
+ comb += cr_b_idx.eq(SVEXTRA.NONE)
+ with m.If(op.sv_cr_in == SVEXTRA.Idx_1_2.value):
+ comb += cr_a_idx.eq(SVEXTRA.Idx1)
+ comb += cr_b_idx.eq(SVEXTRA.Idx2)
+
+ # select the relevant CR bitfields
with m.Switch(self.sel_in):
with m.Case(CRInSel.NONE):
pass # No bitfield activated
with m.Case(CRInSel.CR0):
- comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
+ comb += cr_bf.eq(0) # CR0 (MSB0 numbering)
comb += self.cr_bitfield.ok.eq(1)
with m.Case(CRInSel.BI):
- comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
+ comb += cr_bf.eq(self.dec.BI[2:5])
comb += self.cr_bitfield.ok.eq(1)
with m.Case(CRInSel.BFA):
- comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
+ comb += cr_bf.eq(self.dec.FormX.BFA)
comb += self.cr_bitfield.ok.eq(1)
with m.Case(CRInSel.BA_BB):
- comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
+ comb += cr_bf.eq(self.dec.BA[2:5])
comb += self.cr_bitfield.ok.eq(1)
- comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
+ comb += cr_bf_b.eq(self.dec.BB[2:5])
comb += self.cr_bitfield_b.ok.eq(1)
- comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
+ comb += cr_bf_o.eq(self.dec.BT[2:5])
comb += self.cr_bitfield_o.ok.eq(1)
with m.Case(CRInSel.BC):
- comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
+ comb += cr_bf.eq(self.dec.BC[2:5])
comb += self.cr_bitfield.ok.eq(1)
with m.Case(CRInSel.WHOLE_REG):
comb += self.whole_reg.ok.eq(1)
# otherwise use all of it
comb += self.whole_reg.data.eq(0xff)
+ # now do the SVP64 munging.
+ extra = self.sv_rm.extra # SVP64 extra bits 10:18
+
+ comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
+ comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
+ comb += svdec.cr_in.eq(cr_bf) # 3-bit (BFA)
+
+ comb += svdec_b.extra.eq(extra) # EXTRA field of SVP64 RM
+ comb += svdec_b.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
+ comb += svdec_b.cr_in.eq(cr_bf_b) # 3-bit (BB[2:5])
+
+ comb += svdec_o.extra.eq(extra) # EXTRA field of SVP64 RM
+ comb += svdec_o.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
+ comb += svdec_o.cr_in.eq(cr_bf_o) # 3-bit (BT[2:5])
+
+ # indices are slightly different, BA/BB mess sorted above
+ comb += svdec.idx.eq(cr_a_idx) # SVP64 CR in A
+ comb += svdec_b.idx.eq(cr_b_idx) # SVP64 CR in B
+ comb += svdec_o.idx.eq(op.sv_cr_out) # SVP64 CR out
+
+ # outputs: 7-bit reg number and whether it's vectorised
+ comb += self.cr_bitfield.data.eq(svdec.cr_out)
+ comb += self.cr_isvec.eq(svdec.isvec)
+ comb += self.cr_bitfield_b.data.eq(svdec_b.cr_out)
+ comb += self.cr_b_isvec.eq(svdec_b.isvec)
+ comb += self.cr_bitfield_o.data.eq(svdec_o.cr_out)
+ comb += self.cr_o_isvec.eq(svdec_o.isvec)
+
return m
self.state = state
def get_col_subset(self, do):
- subset = {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
+ subset = {'sv_cr_in', 'sv_cr_out', 'SV_Etype',
+ 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
for k, v in record_names.items():
if hasattr(do, k):
subset.add(v)
subset.add("sv_in2")
subset.add("sv_in3")
subset.add("sv_out")
+ subset.add("sv_cr_in")
+ subset.add("sv_cr_out")
subset.add("SV_Etype")
subset.add("SV_Ptype")
subset.add("lk")
comb += e.write_fast2.eq(dec_o2.fast_out)
# condition registers (CR)
- comb += e.read_cr1.eq(self.dec_cr_in.cr_bitfield)
- comb += e.read_cr2.eq(self.dec_cr_in.cr_bitfield_b)
- comb += e.read_cr3.eq(self.dec_cr_in.cr_bitfield_o)
- comb += e.write_cr.eq(self.dec_cr_out.cr_bitfield)
+ for to_reg, fromreg in (
+ (e.read_cr1, self.dec_cr_in.cr_bitfield),
+ (e.read_cr2, self.dec_cr_in.cr_bitfield_b),
+ (e.read_cr3, self.dec_cr_in.cr_bitfield_o),
+ (e.write_cr, self.dec_cr_out.cr_bitfield)):
+ comb += to_reg.data.eq(fromreg.data)
+ comb += to_reg.ok.eq(fromreg.ok)
# sigh this is exactly the sort of thing for which the
# decoder is designed to not need. MTSPR, MFSPR and others need
projects / soc.git / blobdiff