comment SRR1 mem.exception

[soc.git] / src / soc / decoder / power_decoder2.py

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index b581922b01095f68d19906fcae7dc4969737e0a5..ced6e9f590c18e1d852e822dd8fdbd0a8081d9ee 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -911,22 +911,18 @@ class PowerDecode2(PowerDecodeSubset):
         # after a failed LD/ST.
         with m.If(exc.happened):
             with m.If(exc.alignment):
-                self.trap(m, TT.MEMEXC, 0x600)
+                self.trap(m, TT.PRIV, 0x600)
             with m.Elif(exc.instr_fault):
                 with m.If(exc.segment_fault):
-                    self.trap(m, TT.MEMEXC, 0x480)
+                    self.trap(m, TT.PRIV, 0x480)
                 with m.Else():
-                    # TODO
-                    #srr1(63 - 33) <= exc.invalid;
-                    #srr1(63 - 35) <= exc.perm_error; -- noexec fault
-                    #srr1(63 - 44) <= exc.badtree;
-                    #srr1(63 - 45) <= exc.rc_error;
+                    #spass exception info to trap to create SRR1
                     self.trap(m, TT.MEMEXC, 0x400, exc)
             with m.Else():
                 with m.If(exc.segment_fault):
-                    self.trap(m, TT.MEMEXC, 0x380)
+                    self.trap(m, TT.PRIV, 0x380)
                 with m.Else():
-                    self.trap(m, TT.MEMEXC, 0x300)
+                    self.trap(m, TT.PRIV, 0x300)
 
         # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
         with m.Elif(dec_irq_ok):