from nmutil.iocontrol import RecordObject
from nmutil.extend import exts
+from soc.experiment.mem_types import LDSTException
+
from soc.decoder.power_regspec_map import regspec_decode_read
from soc.decoder.power_regspec_map import regspec_decode_write
from soc.decoder.power_decoder import create_pdecode
m = Module()
comb = m.d.comb
- # update mode LD/ST uses read-reg A also as an output
- with m.If(self.dec.op.upd == LDSTMode.update):
- comb += self.reg_out.eq(self.dec.RA)
- comb += self.reg_out.ok.eq(1)
+ if hasattr(self.dec.op, "upd"):
+ # update mode LD/ST uses read-reg A also as an output
+ with m.If(self.dec.op.upd == LDSTMode.update):
+ comb += self.reg_out.eq(self.dec.RA)
+ comb += self.reg_out.ok.eq(1)
# B, BC or BCREG: potential implicit register (LR) output
# these give bl, bcl, bclrl, etc.
return m
+# dictionary of Input Record field names that, if they exist,
+# will need a corresponding CSV Decoder file column (actually, PowerOp)
+# to be decoded (this includes the single bit names)
+record_names = {'insn_type': 'internal_op',
+ 'fn_unit': 'function_unit',
+ 'rc': 'rc_sel',
+ 'oe': 'rc_sel',
+ 'zero_a': 'in1_sel',
+ 'imm_data': 'in2_sel',
+ 'invert_in': 'inv_a',
+ 'invert_out': 'inv_out',
+ 'rc': 'cr_out',
+ 'oe': 'cr_in',
+ 'output_carry': 'cry_out',
+ 'input_carry': 'cry_in',
+ 'is_32bit': 'is_32b',
+ 'is_signed': 'sgn',
+ 'lk': 'lk',
+ 'data_len': 'ldst_len',
+ 'byte_reverse': 'br',
+ 'sign_extend': 'sgn_ext',
+ 'ldst_mode': 'upd',
+ }
+
class PowerDecodeSubset(Elaboratable):
"""PowerDecodeSubset: dynamic subset decoder
-
"""
+ def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None):
- def __init__(self, dec, opkls=None, fn_name=None, col_subset=None):
+ self.final = final
+ self.opkls = opkls
+ self.fn_name = fn_name
+ self.e = Decode2ToExecute1Type(name=self.fn_name, opkls=self.opkls)
+ col_subset = self.get_col_subset(self.e.do)
+ # create decoder if one not already given
if dec is None:
- self.opkls = opkls
- self.fn_name = fn_name
- self.dec = create_pdecode(name=fn_name, col_subset=col_subset,
+ dec = create_pdecode(name=fn_name, col_subset=col_subset,
row_subset=self.rowsubsetfn)
- else:
- self.dec = dec
- self.opkls = None
- self.fn_name = None
- self.e = Decode2ToExecute1Type(name=self.fn_name, opkls=self.opkls)
+ self.dec = dec
- # state information needed by the Decoder (TODO: this as a Record)
- self.state = CoreState("dec2")
+ # state information needed by the Decoder
+ if state is None:
+ state = CoreState("dec2")
+ self.state = state
+
+ def get_col_subset(self, do):
+ subset = {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
+ for k, v in record_names.items():
+ if hasattr(do, k):
+ subset.add(v)
+ print ("get_col_subset", self.fn_name, do.fields, subset)
+ return subset
def rowsubsetfn(self, opcode, row):
return row['unit'] == self.fn_name
return self.dec.ports() + self.e.ports()
def needs_field(self, field, op_field):
- do = self.e_tmp.do
- return hasattr(do, field) and self.op_get(op_field)
+ if self.final:
+ do = self.e.do
+ else:
+ do = self.e_tmp.do
+ return hasattr(do, field) and self.op_get(op_field) is not None
def do_copy(self, field, val, final=False):
- if final:
+ if final or self.final:
do = self.e.do
else:
do = self.e_tmp.do
comb = m.d.comb
state = self.state
e_out, op, do_out = self.e, self.dec.op, self.e.do
- dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
+ msr, cia = state.msr, state.pc
# fill in for a normal instruction (not an exception)
# copy over if non-exception, non-privileged etc. is detected
- self.e_tmp = e = Decode2ToExecute1Type(name=self.fn_name,
- opkls=self.opkls)
+ if self.final:
+ e = self.e
+ else:
+ if self.fn_name is None:
+ name = "tmp"
+ else:
+ name = self.fn_name + "tmp"
+ self.e_tmp = e = Decode2ToExecute1Type(name=name, opkls=self.opkls)
do = e.do
# set up submodule decoders
m.submodules.dec = self.dec
- m.submodules.dec_ai = dec_ai = DecodeAImm(self.dec)
- m.submodules.dec_bi = dec_bi = DecodeBImm(self.dec)
m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec)
comb += i.eq(self.dec.opcode_in)
# ...and subdecoders' input fields
- comb += dec_ai.sel_in.eq(op.in1_sel)
- comb += dec_bi.sel_in.eq(op.in2_sel)
comb += dec_rc.sel_in.eq(op.rc_sel)
comb += dec_oe.sel_in.eq(op.rc_sel) # XXX should be OE sel
comb += self.dec_cr_in.sel_in.eq(op.cr_in)
comb += self.do_copy("fn_unit", self.op_get("function_unit"))
# immediates
- comb += self.do_copy("imm_data", dec_bi.imm_out) # imm in RB
- comb += self.do_copy("zero_a", dec_ai.immz_out) # RA==0 detected
+ if self.needs_field("zero_a", "in1_sel"):
+ m.submodules.dec_ai = dec_ai = DecodeAImm(self.dec)
+ comb += dec_ai.sel_in.eq(op.in1_sel)
+ comb += self.do_copy("zero_a", dec_ai.immz_out) # RA==0 detected
+ if self.needs_field("imm_data", "in2_sel"):
+ m.submodules.dec_bi = dec_bi = DecodeBImm(self.dec)
+ comb += dec_bi.sel_in.eq(op.in2_sel)
+ comb += self.do_copy("imm_data", dec_bi.imm_out) # imm in RB
# rc and oe out
comb += self.do_copy("rc", dec_rc.rc_out)
comb += self.do_copy("oe", dec_oe.oe_out)
+ # CR in/out
comb += self.do_copy("read_cr_whole", self.dec_cr_in.whole_reg)
comb += self.do_copy("write_cr_whole", self.dec_cr_out.whole_reg)
comb += self.do_copy("write_cr0", self.dec_cr_out.cr_bitfield.ok)
+ comb += self.do_copy("input_cr", self.op_get("cr_in")) # CR in
+ comb += self.do_copy("output_cr", self.op_get("cr_out")) # CR out
+
# decoded/selected instruction flags
comb += self.do_copy("data_len", self.op_get("ldst_len"))
comb += self.do_copy("invert_in", self.op_get("inv_a"))
comb += self.do_copy("sign_extend", self.op_get("sgn_ext"))
comb += self.do_copy("ldst_mode", self.op_get("upd")) # LD/ST mode
- # These should be removed eventually
- comb += self.do_copy("input_cr", self.op_get("cr_in")) # CR in
- comb += self.do_copy("output_cr", self.op_get("cr_out")) # CR out
-
return m
instructions are illegal (or privileged) or not, and instead of
just leaving at that, *replacing* the instruction to execute with
a suitable alternative (trap).
+
+ LDSTExceptions are done the cycle _after_ they're detected (after
+ they come out of LDSTCompUnit). basically despite the instruction
+ being decoded, the results of the decode are completely ignored
+ and "exception.happened" used to set the "actual" instruction to
+ "OP_TRAP". the LDSTException data structure gets filled in,
+ in the CompTrapOpSubset and that's what it fills in SRR.
+
+ to make this work, TestIssuer must notice "exception.happened"
+ after the (failed) LD/ST and copies the LDSTException info from
+ the output, into here (PowerDecoder2). without incrementing PC.
"""
+ def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None):
+ super().__init__(dec, opkls, fn_name, final, state)
+ self.exc = LDSTException("dec2_exc")
+
+ def get_col_subset(self, opkls):
+ subset = super().get_col_subset(opkls)
+ subset.add("in1_sel")
+ subset.add("asmcode")
+ subset.add("in2_sel")
+ subset.add("in3_sel")
+ subset.add("out_sel")
+ subset.add("lk")
+ subset.add("internal_op")
+ subset.add("form")
+ return subset
+
def elaborate(self, platform):
m = super().elaborate(platform)
comb = m.d.comb
# set the trapaddr to 0x700 for a td/tw/tdi/twi operation
with m.If(op.internal_op == MicrOp.OP_TRAP):
# *DO NOT* call self.trap here. that would reset absolutely
- # rverything including destroying read of RA and RB.
- comb += self.do_copy("trapaddr", 0x70, True) # strip first nibble
+ # everything including destroying read of RA and RB.
+ comb += self.do_copy("trapaddr", 0x70) # strip first nibble
+
+ ####################
+ # ok so the instruction's been decoded, blah blah, however
+ # now we need to determine if it's actually going to go ahead...
+ # *or* if in fact it's a privileged operation, whether there's
+ # an external interrupt, etc. etc. this is a simple priority
+ # if-elif-elif sequence. decrement takes highest priority,
+ # EINT next highest, privileged operation third.
# check if instruction is privileged
is_priv_insn = instr_is_priv(m, op.internal_op, e.do.insn)
- # external interrupt? only if MSR.EE set
- with m.If(ext_irq & msr[MSR.EE]): # v3.0B p944 (MSR.EE)
- self.trap(m, TT.EINT, 0x500)
+ # different IRQ conditions
+ ext_irq_ok = Signal()
+ dec_irq_ok = Signal()
+ priv_ok = Signal()
+ illeg_ok = Signal()
+ exc = self.exc
+
+ comb += ext_irq_ok.eq(ext_irq & msr[MSR.EE]) # v3.0B p944 (MSR.EE)
+ comb += dec_irq_ok.eq(dec_spr[63] & msr[MSR.EE]) # 6.5.11 p1076
+ comb += priv_ok.eq(is_priv_insn & msr[MSR.PR])
+ comb += illeg_ok.eq(op.internal_op == MicrOp.OP_ILLEGAL)
+
+ # LD/ST exceptions. TestIssuer copies the exception info at us
+ # after a failed LD/ST.
+ with m.If(exc.happened):
+ with m.If(exc.alignment):
+ self.trap(m, TT.PRIV, 0x600)
+ with m.Elif(exc.instr_fault):
+ with m.If(exc.segment_fault):
+ self.trap(m, TT.PRIV, 0x480)
+ with m.Else():
+ #spass exception info to trap to create SRR1
+ self.trap(m, TT.MEMEXC, 0x400, exc)
+ with m.Else():
+ with m.If(exc.segment_fault):
+ self.trap(m, TT.PRIV, 0x380)
+ with m.Else():
+ self.trap(m, TT.PRIV, 0x300)
# decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
- with m.If(dec_spr[63] & msr[MSR.EE]): # v3.0B 6.5.11 p1076
+ with m.Elif(dec_irq_ok):
self.trap(m, TT.DEC, 0x900) # v3.0B 6.5 p1065
+ # external interrupt? only if MSR.EE set
+ with m.Elif(ext_irq_ok):
+ self.trap(m, TT.EINT, 0x500)
+
# privileged instruction trap
- with m.Elif(is_priv_insn & msr[MSR.PR]):
+ with m.Elif(priv_ok):
self.trap(m, TT.PRIV, 0x700)
# illegal instruction must redirect to trap. this is done by
# *overwriting* the decoded instruction and starting again.
# (note: the same goes for interrupts and for privileged operations,
# just with different trapaddr and traptype)
- with m.Elif(op.internal_op == MicrOp.OP_ILLEGAL):
+ with m.Elif(illeg_ok):
# illegal instruction trap
self.trap(m, TT.ILLEG, 0x700)
with m.Else():
comb += e_out.eq(e)
+ ####################
+ # follow-up after trap/irq to set up SRR0/1
+
# trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
# Note: OP_SC could actually be modified to just be a trap
with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
comb += e_out.read_fast2.data.eq(FastRegs.SRR1) # constant: SRR1
comb += e_out.read_fast2.ok.eq(1)
+ # annoying simulator bug
+ if hasattr(e_out, "asmcode") and hasattr(self.dec.op, "asmcode"):
+ comb += e_out.asmcode.eq(self.dec.op.asmcode)
+
return m
- def trap(self, m, traptype, trapaddr):
+ def trap(self, m, traptype, trapaddr, exc=None):
"""trap: this basically "rewrites" the decoded instruction as a trap
"""
comb = m.d.comb
comb += self.do_copy("fn_unit", Function.TRAP, True)
comb += self.do_copy("trapaddr", trapaddr >> 4, True) # bottom 4 bits
comb += self.do_copy("traptype", traptype, True) # request type
+ comb += self.do_copy("ldst_exc", exc, True) # request type
comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state"
comb += self.do_copy("cia", self.state.pc, True) # copy of PC "state"
projects / soc.git / blobdiff