start on SVP64 RM Mode decoder

[soc.git] / src / soc / decoder / power_enums.py

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 10357bd710ce0f0621d162a949cbf236784d0b0f..1254534d41aaa3e5ece31c8f2bafa21229f035f9 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -111,6 +111,7 @@ class Form(Enum):
     EVS = 26
     Z22 = 27
     Z23 = 28
+    SVL = 29 # Simple-V for setvl instruction
 
 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 
@@ -135,6 +136,12 @@ class SVEXTRA(Enum):
     Idx3 = 4
     Idx_1_2 = 5 # due to weird BA/BB for crops
 
+@unique
+class SVP64PredMode(Enum):
+    ALWAYS = 0
+    INT = 1
+    CR = 2
+
 @unique
 class SVP64PredInt(Enum):
     ALWAYS = 0
@@ -179,6 +186,13 @@ class SVP64subvl(Enum):
     VEC3 = 2
     VEC4 = 3
 
+@unique
+class SVP64sat(Enum):
+    NONE = 0
+    SIGNED = 1
+    UNSIGNED = 2
+
+
 # supported instructions: make sure to keep up-to-date with CSV files
 # just like everything else
 _insns = [