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add ability to set and distinguish RT=0 (RT_OR_ZERO) to OutSel enum
[soc.git]
/
src
/
soc
/
decoder
/
power_enums.py
diff --git
a/src/soc/decoder/power_enums.py
b/src/soc/decoder/power_enums.py
index 1254534d41aaa3e5ece31c8f2bafa21229f035f9..a823295c976b45b7e01db1a9603814b769543496 100644
(file)
--- a/
src/soc/decoder/power_enums.py
+++ b/
src/soc/decoder/power_enums.py
@@
-352,6
+352,7
@@
class OutSel(Enum):
RT = 1
RA = 2
SPR = 3
+ RT_OR_ZERO = 4
@unique