radix: reading first page table entry

[soc.git] / src / soc / decoder / power_enums.py

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 46e97d6964aaa0a7fb5e91964036126cc336b441..1254534d41aaa3e5ece31c8f2bafa21229f035f9 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -2,6 +2,14 @@
 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 # Copyright (C) 2020, Michael Nolan
 
+"""Enums used in OpenPOWER ISA decoding
+
+Note: for SV, from v3.1B p12:
+
+    The designated SPR sandbox consists of non-privileged SPRs 704-719 and
+    privileged SPRs 720-735.
+"""
+
 from enum import Enum, unique
 import csv
 import os
@@ -103,6 +111,7 @@ class Form(Enum):
     EVS = 26
     Z22 = 27
     Z23 = 28
+    SVL = 29 # Simple-V for setvl instruction
 
 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 
@@ -127,6 +136,63 @@ class SVEXTRA(Enum):
     Idx3 = 4
     Idx_1_2 = 5 # due to weird BA/BB for crops
 
+@unique
+class SVP64PredMode(Enum):
+    ALWAYS = 0
+    INT = 1
+    CR = 2
+
+@unique
+class SVP64PredInt(Enum):
+    ALWAYS = 0
+    R3_UNARY = 1
+    R3 = 2
+    R3_N = 3
+    R10 = 4
+    R10_N = 5
+    R30 = 6
+    R30_N = 7
+
+@unique
+class SVP64PredCR(Enum):
+    LT = 0
+    GE = 1
+    GT = 2
+    LE = 3
+    EQ = 4
+    NE = 5
+    SO = 6
+    NS = 7
+
+@unique
+class SVP64RMMode(Enum):
+    NORMAL = 0
+    MAPREDUCE = 1
+    FFIRST = 2
+    SATURATE = 3
+    PREDRES = 4
+
+@unique
+class SVP64width(Enum):
+    DEFAULT = 0
+    EW_32 = 1
+    EW_16 = 2
+    EW_8 = 3
+
+@unique
+class SVP64subvl(Enum):
+    VEC1 = 0
+    VEC2 = 1
+    VEC3 = 2
+    VEC4 = 3
+
+@unique
+class SVP64sat(Enum):
+    NONE = 0
+    SIGNED = 1
+    UNSIGNED = 2
+
+
 # supported instructions: make sure to keep up-to-date with CSV files
 # just like everything else
 _insns = [