radix: reading first page table entry

[soc.git] / src / soc / decoder / power_enums.py

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index bc7d8248e2fd2fae452938c466301cae330adbff..1254534d41aaa3e5ece31c8f2bafa21229f035f9 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -1,3 +1,15 @@
+# SPDX-License: LGPLv3+
+# Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+# Copyright (C) 2020, Michael Nolan
+
+"""Enums used in OpenPOWER ISA decoding
+
+Note: for SV, from v3.1B p12:
+
+    The designated SPR sandbox consists of non-privileged SPRs 704-719 and
+    privileged SPRs 720-735.
+"""
+
 from enum import Enum, unique
 import csv
 import os
@@ -5,6 +17,13 @@ from os.path import dirname, join
 from collections import namedtuple
 
 
+def find_wiki_dir():
+    filedir = os.path.dirname(os.path.abspath(__file__))
+    basedir = dirname(dirname(dirname(filedir)))
+    tabledir = join(basedir, 'libreriscv')
+    tabledir = join(tabledir, 'openpower')
+    return join(tabledir, 'isatables')
+
 def find_wiki_file(name):
     filedir = os.path.dirname(os.path.abspath(__file__))
     basedir = dirname(dirname(dirname(filedir)))
@@ -12,8 +31,7 @@ def find_wiki_file(name):
     tabledir = join(tabledir, 'openpower')
     tabledir = join(tabledir, 'isatables')
 
-    file_path = join(tabledir, name)
-    return file_path
+    return join(find_wiki_dir(), name)
 
 
 def get_csv(name):
@@ -58,6 +76,8 @@ class Function(Enum):
     MUL = 1 << 8
     DIV = 1 << 9
     SPR = 1 << 10
+    MMU = 1 << 11
+    SV = 1 << 12 # Simple-V https://libre-soc.org/openpower/sv
 
 
 @unique
@@ -91,6 +111,86 @@ class Form(Enum):
     EVS = 26
     Z22 = 27
     Z23 = 28
+    SVL = 29 # Simple-V for setvl instruction
+
+# Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
+
+@unique
+class SVPtype(Enum):
+    NONE = 0
+    P1 = 1
+    P2 = 2
+
+@unique
+class SVEtype(Enum):
+    NONE = 0
+    EXTRA2 = 1
+    EXTRA3 = 2
+
+@unique
+class SVEXTRA(Enum):
+    NONE = 0
+    Idx0 = 1
+    Idx1 = 2
+    Idx2 = 3
+    Idx3 = 4
+    Idx_1_2 = 5 # due to weird BA/BB for crops
+
+@unique
+class SVP64PredMode(Enum):
+    ALWAYS = 0
+    INT = 1
+    CR = 2
+
+@unique
+class SVP64PredInt(Enum):
+    ALWAYS = 0
+    R3_UNARY = 1
+    R3 = 2
+    R3_N = 3
+    R10 = 4
+    R10_N = 5
+    R30 = 6
+    R30_N = 7
+
+@unique
+class SVP64PredCR(Enum):
+    LT = 0
+    GE = 1
+    GT = 2
+    LE = 3
+    EQ = 4
+    NE = 5
+    SO = 6
+    NS = 7
+
+@unique
+class SVP64RMMode(Enum):
+    NORMAL = 0
+    MAPREDUCE = 1
+    FFIRST = 2
+    SATURATE = 3
+    PREDRES = 4
+
+@unique
+class SVP64width(Enum):
+    DEFAULT = 0
+    EW_32 = 1
+    EW_16 = 2
+    EW_8 = 3
+
+@unique
+class SVP64subvl(Enum):
+    VEC1 = 0
+    VEC2 = 1
+    VEC3 = 2
+    VEC4 = 3
+
+@unique
+class SVP64sat(Enum):
+    NONE = 0
+    SIGNED = 1
+    UNSIGNED = 2
 
 
 # supported instructions: make sure to keep up-to-date with CSV files
@@ -116,7 +216,9 @@ _insns = [
     "nand", "neg", "nego", "nop", "nor", "or", "orc", "ori", "oris",
     "popcntb", "popcntd", "popcntw", "prtyd", "prtyw", "rfid", "rldcl",
     "rldcr", "rldic", "rldicl", "rldicr", "rldimi", "rlwimi", "rlwinm",
-    "rlwnm", "setb", "sim_cfg", "slbia", "sld", "slw", "srad", "sradi", "sraw",
+    "rlwnm", "setb",
+    "setvl", # https://libre-soc.org/openpower/sv/setvl
+    "sim_cfg", "slbia", "sld", "slw", "srad", "sradi", "sraw",
     "srawi", "srd", "srw", "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
     "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx", "sth", "sthbrx", "sthcx",
     "sthu", "sthux", "sthx", "stw", "stwbrx", "stwcx", "stwu", "stwux",
@@ -293,6 +395,7 @@ class CRInSel(Enum):
     BA_BB = 4
     BC = 5
     WHOLE_REG = 6
+    CR1 = 7
 
 
 @unique
@@ -302,6 +405,7 @@ class CROutSel(Enum):
     BF = 2
     BT = 3
     WHOLE_REG = 4
+    CR1 = 5
 
 
 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and