start adding svp64 enums

[soc.git] / src / soc / decoder / power_enums.py

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 743203653d942cdfc2068102e31d136d740766ab..74c149e3b5cc5e45d8212b879ebb8ce74128be2e 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -1,3 +1,7 @@
+# SPDX-License: LGPLv3+
+# Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+# Copyright (C) 2020, Michael Nolan
+
 from enum import Enum, unique
 import csv
 import os
@@ -5,6 +9,13 @@ from os.path import dirname, join
 from collections import namedtuple
 
 
+def find_wiki_dir():
+    filedir = os.path.dirname(os.path.abspath(__file__))
+    basedir = dirname(dirname(dirname(filedir)))
+    tabledir = join(basedir, 'libreriscv')
+    tabledir = join(tabledir, 'openpower')
+    return join(tabledir, 'isatables')
+
 def find_wiki_file(name):
     filedir = os.path.dirname(os.path.abspath(__file__))
     basedir = dirname(dirname(dirname(filedir)))
@@ -12,8 +23,7 @@ def find_wiki_file(name):
     tabledir = join(tabledir, 'openpower')
     tabledir = join(tabledir, 'isatables')
 
-    file_path = join(tabledir, name)
-    return file_path
+    return join(find_wiki_dir(), name)
 
 
 def get_csv(name):
@@ -59,6 +69,7 @@ class Function(Enum):
     DIV = 1 << 9
     SPR = 1 << 10
     MMU = 1 << 11
+    SV = 1 << 12 # Simple-V https://libre-soc.org/openpower/sv
 
 
 @unique
@@ -93,6 +104,19 @@ class Form(Enum):
     Z22 = 27
     Z23 = 28
 
+# Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
+
+@unique
+class SVPtype(Enum):
+    NONE = 0
+    P1 = 1
+    P2 = 2
+
+@unique
+class SVEtype(Enum):
+    NONE = 0
+    EXTRA2 = 1
+    EXTRA3 = 2
 
 # supported instructions: make sure to keep up-to-date with CSV files
 # just like everything else
@@ -117,7 +141,9 @@ _insns = [
     "nand", "neg", "nego", "nop", "nor", "or", "orc", "ori", "oris",
     "popcntb", "popcntd", "popcntw", "prtyd", "prtyw", "rfid", "rldcl",
     "rldcr", "rldic", "rldicl", "rldicr", "rldimi", "rlwimi", "rlwinm",
-    "rlwnm", "setb", "sim_cfg", "slbia", "sld", "slw", "srad", "sradi", "sraw",
+    "rlwnm", "setb",
+    "setvl", # https://libre-soc.org/openpower/sv/setvl
+    "sim_cfg", "slbia", "sld", "slw", "srad", "sradi", "sraw",
     "srawi", "srd", "srw", "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
     "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx", "sth", "sthbrx", "sthcx",
     "sthu", "sthux", "sthx", "stw", "stwbrx", "stwcx", "stwu", "stwux",
@@ -294,6 +320,7 @@ class CRInSel(Enum):
     BA_BB = 4
     BC = 5
     WHOLE_REG = 6
+    CR1 = 7
 
 
 @unique
@@ -303,6 +330,7 @@ class CROutSel(Enum):
     BF = 2
     BT = 3
     WHOLE_REG = 4
+    CR1 = 5
 
 
 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and