+# SPDX-License: LGPLv3+
+# Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+# Copyright (C) 2020, Michael Nolan
+
from enum import Enum, unique
import csv
import os
from collections import namedtuple
+def find_wiki_dir():
+ filedir = os.path.dirname(os.path.abspath(__file__))
+ basedir = dirname(dirname(dirname(filedir)))
+ tabledir = join(basedir, 'libreriscv')
+ tabledir = join(tabledir, 'openpower')
+ return join(tabledir, 'isatables')
+
def find_wiki_file(name):
filedir = os.path.dirname(os.path.abspath(__file__))
basedir = dirname(dirname(dirname(filedir)))
tabledir = join(tabledir, 'openpower')
tabledir = join(tabledir, 'isatables')
- file_path = join(tabledir, name)
- return file_path
+ return join(find_wiki_dir(), name)
def get_csv(name):
MUL = 1 << 8
DIV = 1 << 9
SPR = 1 << 10
+ MMU = 1 << 11
+ SV = 1 << 12 # Simple-V https://libre-soc.org/openpower/sv
@unique
Z22 = 27
Z23 = 28
+# Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
+
+@unique
+class SVPtype(Enum):
+ NONE = 0
+ P1 = 1
+ P2 = 2
+
+@unique
+class SVEtype(Enum):
+ NONE = 0
+ EXTRA2 = 1
+ EXTRA3 = 2
# supported instructions: make sure to keep up-to-date with CSV files
# just like everything else
"lbarx", "lbz", "lbzu", "lbzux", "lbzx", "ld", "ldarx", "ldbrx",
"ldu", "ldux", "ldx", "lha", "lharx", "lhau", "lhaux", "lhax",
"lhbrx", "lhz", "lhzu", "lhzux", "lhzx", "lwa", "lwarx", "lwaux",
- "lwax", "lwbrx", "lwz", "lwzu", "lwzux", "lwzx", "mcrf", "mcrxr",
+ "lwax", "lwbrx", "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", "mcrf", "mcrxr",
"mcrxrx", "mfcr/mfocrf", "mfmsr", "mfspr", "modsd", "modsw", "modud",
"moduw", "mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr", "mulhd", "mulhdu",
"mulhw", "mulhwu", "mulld", "mulldo", "mulli", "mullw", "mullwo",
"nand", "neg", "nego", "nop", "nor", "or", "orc", "ori", "oris",
"popcntb", "popcntd", "popcntw", "prtyd", "prtyw", "rfid", "rldcl",
"rldcr", "rldic", "rldicl", "rldicr", "rldimi", "rlwimi", "rlwinm",
- "rlwnm", "setb", "sim_cfg", "sld", "slw", "srad", "sradi", "sraw",
- "srawi", "srd", "srw", "stb", "stbcx", "stbu", "stbux", "stbx", "std",
- "stdbrx", "stdcx", "stdu", "stdux", "stdx", "sth", "sthbrx", "sthcx",
+ "rlwnm", "setb",
+ "setvl", # https://libre-soc.org/openpower/sv/setvl
+ "sim_cfg", "slbia", "sld", "slw", "srad", "sradi", "sraw",
+ "srawi", "srd", "srw", "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
+ "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx", "sth", "sthbrx", "sthcx",
"sthu", "sthux", "sthx", "stw", "stwbrx", "stwcx", "stwu", "stwux",
"stwx", "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
"subfme", "subfmeo", "subfo", "subfze", "subfzeo", "sync", "td",
- "tdi", "tw", "twi", "xor", "xori", "xoris",
+ "tdi", "tlbie", "tlbiel", "tw", "twi", "xor", "xori", "xoris",
]
# two-way lookup of instruction-to-index and vice-versa
OP_MTMSRD = 72
OP_SC = 73
OP_MTMSR = 74
+ OP_TLBIE = 75
@unique
ZERO = 0
ONE = 1
CA = 2
+ # TODO OV = 3
@unique
BA_BB = 4
BC = 5
WHOLE_REG = 6
+ CR1 = 7
@unique
BF = 2
BT = 3
WHOLE_REG = 4
+ CR1 = 5
# SPRs - Special-Purpose Registers. See V3.0B Figure 18 p971 and
print(SPR.__members__['TAR'])
for x in SPR:
print(x, x.value, str(x), x.name)
+
+ print ("function", Function.ALU.name)