add OP_SC

[soc.git] / src / soc / decoder / power_enums.py

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 1b8395cc1a49f7937c814eeeae9c464ed1b3717a..f179f2cecd97ea5fbcf2b1b6d59f0025ef2a654b 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -23,13 +23,14 @@ def get_csv(name):
 
 
 # names of the fields in the tables that don't correspond to an enum
-single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out',
+single_bit_flags = ['inv A', 'inv out',
                     'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b',
                     'sgn', 'lk', 'sgl pipe']
 
 # default values for fields in the table
 default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
                   'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
+                  'CR in': 'NONE',
                   'ldst len': 'NONE',
                   'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
 
@@ -45,15 +46,15 @@ def get_signal_name(name):
 @unique
 class Function(Enum):
     NONE = 0
-    ALU = 1
-    LDST = 2
-    SHIFT_ROT = 3
-    LOGICAL = 4
-    BRANCH = 5
-    CR = 6
-    TRAP = 7
-    MUL = 8
-    DIV = 9
+    ALU = 1<<1
+    LDST = 1<<2
+    SHIFT_ROT = 1<<3
+    LOGICAL = 1<<4
+    BRANCH = 1<<5
+    CR = 1<<6
+    TRAP = 1<<7
+    MUL = 1<<8
+    DIV = 1<<9
 
 
 @unique
@@ -88,6 +89,44 @@ class Form(Enum):
     Z22 = 27
     Z23 = 28
 
+# supported instructions: make sure to keep up-to-date with CSV files
+# just like everything else
+_insns = [
+    "NONE", "add", "addc", "addco", "adde", "addeo", "addi", "addic", "addic.",
+    "addis", "addme", "addmeo", "addo", "addze", "addzeo", "and", "andc",
+    "andi.", "andis.", "attn", "b", "bc", "bcctr", "bclr", "bctar",
+    "bpermd", "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
+    "cntlzd", "cntlzw", "cnttzd", "cnttzw", "crand", "crandc", "creqv",
+    "crnand", "crnor", "cror", "crorc", "crxor", "darn", "dcbf", "dcbst",
+    "dcbt", "dcbtst", "dcbz", "divd", "divde", "divdeo", "divdeu",
+    "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
+    "divweu", "divweuo", "divwo", "divwu", "divwuo", "eqv", "extsb",
+    "extsh", "extsw", "extswsli", "icbi", "icbt", "isel", "isync",
+    "lbarx", "lbz", "lbzu", "lbzux", "lbzx", "ld", "ldarx", "ldbrx",
+    "ldu", "ldux", "ldx", "lha", "lharx", "lhau", "lhaux", "lhax",
+    "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", "lwa", "lwarx", "lwaux",
+    "lwax", "lwbrx", "lwz", "lwzu", "lwzux", "lwzx", "mcrf", "mcrxr",
+    "mcrxrx", "mfcr/mfocrf", "mfmsr", "mfspr", "modsd", "modsw", "modud",
+    "moduw", "mtcrf/mtocrf", "mtmsrd", "mtspr", "mulhd", "mulhdu",
+    "mulhw", "mulhwu", "mulld", "mulldo", "mulli", "mullw", "mullwo",
+    "nand", "neg", "nego", "nop", "nor", "or", "orc", "ori", "oris",
+    "popcntb", "popcntd", "popcntw", "prtyd", "prtyw", "rfid", "rldcl",
+    "rldcr", "rldic", "rldicl", "rldicr", "rldimi", "rlwimi", "rlwinm",
+    "rlwnm", "setb", "sim_cfg", "sld", "slw", "srad", "sradi", "sraw",
+    "srawi", "srd", "srw", "stb", "stbcx", "stbu", "stbux", "stbx", "std",
+    "stdbrx", "stdcx", "stdu", "stdux", "stdx", "sth", "sthbrx", "sthcx",
+    "sthu", "sthux", "sthx", "stw", "stwbrx", "stwcx", "stwu", "stwux",
+    "stwx", "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
+    "subfme", "subfmeo", "subfo", "subfze", "subfzeo", "sync", "td",
+    "tdi", "tw", "twi", "xor", "xori", "xoris",
+]
+
+# two-way lookup of instruction-to-index and vice-versa
+insns = {}
+asmidx = {}
+for i, insn in enumerate(_insns):
+    insns[i] = insn
+    asmidx[insn] = i
 
 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
 @unique
@@ -160,6 +199,9 @@ class InternalOp(Enum):
     OP_SIM_CONFIG = 68
     OP_CROP = 69
     OP_RFID = 70
+    OP_MFMSR = 71
+    OP_MTMSRD = 72
+    OP_SC = 73
 
 
 @unique
@@ -168,6 +210,7 @@ class In1Sel(Enum):
     RA = 1
     RA_OR_ZERO = 2
     SPR = 3
+    RS = 4  # for some ALU/Logical operations
 
 
 @unique
@@ -185,12 +228,14 @@ class In2Sel(Enum):
     CONST_SH = 10
     CONST_SH32 = 11
     SPR = 12
+    RS = 13 # for shiftrot (M-Form)
 
 
 @unique
 class In3Sel(Enum):
     NONE = 0
     RS = 1
+    RB = 2 # for shiftrot (M-Form)
 
 
 @unique
@@ -206,8 +251,8 @@ class LdstLen(Enum):
     NONE = 0
     is1B = 1
     is2B = 2
-    is4B = 3
-    is8B = 4
+    is4B = 4
+    is8B = 8
 
 
 @unique
@@ -223,6 +268,24 @@ class CryIn(Enum):
     ONE = 1
     CA = 2
 
+@unique
+class CRInSel(Enum):
+    NONE = 0
+    CR0 = 1
+    BI = 2
+    BFA = 3
+    BA_BB = 4
+    BC = 5
+    WHOLE_REG = 6
+
+@unique
+class CROutSel(Enum):
+    NONE = 0
+    CR0 = 1
+    BF = 2
+    BT = 3
+    WHOLE_REG = 4
+
 
 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
 # http://libre-riscv.org/openpower/isatables/sprs.csv
@@ -246,3 +309,12 @@ XER_bits = {
     'OV32': 44,
     'CA32': 45
     }
+
+if __name__ == '__main__':
+    # find out what the heck is in SPR enum :)
+    print ("sprs", len(SPR))
+    print (dir(SPR))
+    print (dir(Enum))
+    print (SPR.__members__['TAR'])
+    for x in SPR:
+        print (x, x.value, str(x), x.name)