radix: reading first page table entry

[soc.git] / src / soc / decoder / power_fieldsn.py

diff --git a/src/soc/decoder/power_fieldsn.py b/src/soc/decoder/power_fieldsn.py
index 74fcd00733f0175bd36c31f5b9c8097afbf6548a..852dd15b079cc88a1b555f71d216107ce2d9c7a1 100644 (file)
--- a/src/soc/decoder/power_fieldsn.py
+++ b/src/soc/decoder/power_fieldsn.py
@@ -2,6 +2,7 @@ from collections import OrderedDict
 from soc.decoder.power_fields import DecodeFields, BitRange
 from nmigen import Module, Elaboratable, Signal, Cat
 from nmigen.cli import rtlil
+from copy import deepcopy
 
 
 class SignalBitRange(BitRange):
@@ -9,8 +10,17 @@ class SignalBitRange(BitRange):
         BitRange.__init__(self)
         self.signal = signal
 
+    def __deepcopy__(self, memo):
+        signal = deepcopy(self.signal, memo)
+        retval = SignalBitRange(signal=signal)
+        for k, v in self.items():
+            k = deepcopy(k, memo)
+            v = deepcopy(v, memo)
+            retval[k] = v
+        return retval
+
     def _rev(self, k):
-        width = self.signal.shape()[0]
+        width = self.signal.width
         return width-1-k
 
     def __getitem__(self, subs):
@@ -29,17 +39,16 @@ class SignalBitRange(BitRange):
             if stop < 0:
                 stop = len(self) + stop + 1
             for t in range(start, stop, step):
-                t = len(self) - 1 - t # invert field back
+                t = len(self) - 1 - t  # invert field back
                 k = OrderedDict.__getitem__(self, t)
-                res.append(self.signal[self._rev(k)]) # reverse-order here
+                res.append(self.signal[self._rev(k)])  # reverse-order here
             return Cat(*res)
         else:
             if subs < 0:
                 subs = len(self) + subs
-            subs = len(self) - 1 - subs # invert field back
+            subs = len(self) - 1 - subs  # invert field back
             k = OrderedDict.__getitem__(self, subs)
-            return self.signal[self._rev(k)] # reverse-order here
-
+            return self.signal[self._rev(k)]  # reverse-order here
 
 
 class SigDecode(Elaboratable):
@@ -57,13 +66,14 @@ class SigDecode(Elaboratable):
     def ports(self):
         return [self.opcode_in]
 
+
 def create_sigdecode():
     s = SigDecode(32)
     return s
 
+
 if __name__ == '__main__':
     sigdecode = create_sigdecode()
     vl = rtlil.convert(sigdecode, ports=sigdecode.ports())
     with open("decoder.il", "w") as f:
         f.write(vl)
-