radix: reading first page table entry

[soc.git] / src / soc / decoder / power_fieldsn.py

diff --git a/src/soc/decoder/power_fieldsn.py b/src/soc/decoder/power_fieldsn.py
index a5e03a114ec54d915deb13f20c99e8ab59078dc5..852dd15b079cc88a1b555f71d216107ce2d9c7a1 100644 (file)
--- a/src/soc/decoder/power_fieldsn.py
+++ b/src/soc/decoder/power_fieldsn.py
@@ -2,6 +2,7 @@ from collections import OrderedDict
 from soc.decoder.power_fields import DecodeFields, BitRange
 from nmigen import Module, Elaboratable, Signal, Cat
 from nmigen.cli import rtlil
+from copy import deepcopy
 
 
 class SignalBitRange(BitRange):
@@ -9,14 +10,23 @@ class SignalBitRange(BitRange):
         BitRange.__init__(self)
         self.signal = signal
 
+    def __deepcopy__(self, memo):
+        signal = deepcopy(self.signal, memo)
+        retval = SignalBitRange(signal=signal)
+        for k, v in self.items():
+            k = deepcopy(k, memo)
+            v = deepcopy(v, memo)
+            retval[k] = v
+        return retval
+
+    def _rev(self, k):
+        width = self.signal.width
+        return width-1-k
+
     def __getitem__(self, subs):
         # *sigh* field numberings are bit-inverted.  PowerISA 3.0B section 1.3.2
-        width = self.signal.shape()[0]
-        print (dir(self))
-        print (self.items())
         if isinstance(subs, slice):
             res = []
-            print (subs)
             start, stop, step = subs.start, subs.stop, subs.step
             if step is None:
                 step = 1
@@ -25,20 +35,20 @@ class SignalBitRange(BitRange):
             if stop is None:
                 stop = -1
             if start < 0:
-                start = len(self) - start - 1
+                start = len(self) + start + 1
             if stop < 0:
-                stop = len(self) - stop - 1
-            print ("range", start, stop, step)
+                stop = len(self) + stop + 1
             for t in range(start, stop, step):
+                t = len(self) - 1 - t  # invert field back
                 k = OrderedDict.__getitem__(self, t)
-                print ("t", t, k)
-                res.append(self.signal[width-k-1])
+                res.append(self.signal[self._rev(k)])  # reverse-order here
             return Cat(*res)
         else:
+            if subs < 0:
+                subs = len(self) + subs
+            subs = len(self) - 1 - subs  # invert field back
             k = OrderedDict.__getitem__(self, subs)
-            return self.signal[width-k-1]
-
-        print ("translated", subs, translated)
+            return self.signal[self._rev(k)]  # reverse-order here
 
 
 class SigDecode(Elaboratable):
@@ -47,28 +57,23 @@ class SigDecode(Elaboratable):
         self.opcode_in = Signal(width, reset_less=False)
         self.df = DecodeFields(SignalBitRange, [self.opcode_in])
         self.df.create_specs()
-        self.x_s = Signal(len(self.df.FormX.S), reset_less=True)
-        self.x_sh = Signal(len(self.df.FormX.SH), reset_less=True)
-        self.dq_xs_s = Signal(len(self.df.FormDQ.SX_S), reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
-        comb += self.x_s.eq(self.df.FormX.S[0])
-        comb += self.x_sh.eq(self.df.FormX.SH[0:-1])
-        comb += self.dq_xs_s.eq(self.df.FormDQ.SX_S[0:-1])
         return m
 
     def ports(self):
-        return [self.opcode_in, self.x_s, self.x_sh]
+        return [self.opcode_in]
+
 
 def create_sigdecode():
     s = SigDecode(32)
     return s
 
+
 if __name__ == '__main__':
     sigdecode = create_sigdecode()
     vl = rtlil.convert(sigdecode, ports=sigdecode.ports())
     with open("decoder.il", "w") as f:
         f.write(vl)
-