radix: reading first page table entry

[soc.git] / src / soc / decoder / power_regspec_map.py

diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index 65caf014946696c9c8c523a87c0d24ab300b42a7..05ff4814e2504e3acbc5924b614031b460f8bd7c 100644 (file)
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -77,10 +77,10 @@ def regspec_decode_read(e, regfile, name):
         if name == 'xer_so':
             # SO needs to be read for overflow *and* for creation
             # of CR0 and also for MFSPR
-            return ((e.do.oe.oe[0] & e.do.oe.oe_ok) | (e.xer_in & SO == SO)|
+            return ((e.do.oe.oe[0] & e.do.oe.ok) | (e.xer_in & SO == SO)|
                      (e.do.rc.rc & e.do.rc.ok)), SO
         if name == 'xer_ov':
-            return ((e.do.oe.oe[0] & e.do.oe.oe_ok) |
+            return ((e.do.oe.oe[0] & e.do.oe.ok) |
                     (e.xer_in & CA == CA)), OV
         if name == 'xer_ca':
             return ((e.do.input_carry == CryIn.CA.value) |
@@ -91,7 +91,7 @@ def regspec_decode_read(e, regfile, name):
     if regfile == 'STATE':
         # STATE register numbering is *unary* encoded
         PC = 1<<StateRegs.PC
-        MSR = 1<<Stateegs.MSR
+        MSR = 1<<StateRegs.MSR
         if name in ['cia', 'nia']:
             return Const(1), PC # TODO: detect read-conditions
         if name == 'msr':