# dummy (blank) fields, first
entry.update({'EXTRA0': '0', 'EXTRA1': '0', 'EXTRA2': '0',
'EXTRA3': '0',
- 'SV_Ptype': 'NONE', 'SV_Etype': 'NONE'})
+ 'SV_Ptype': 'NONE', 'SV_Etype': 'NONE',
+ 'sv_cr_in': 'NONE', 'sv_cr_out': 'NONE'})
+ for fname in ['in1', 'in2', 'in3', 'out']:
+ entry['sv_%s' % fname] = 'NONE'
# is this SVP64-augmented?
asmcode = entry['comment']
# of the in1/2/3 and CR in/out with the EXTRA0-3 fields
decode = decode_extra(entry, "EXTRA")
dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
-
+
# now examine in1/2/3/out, create sv_in1/2/3/out
for fname in ['in1', 'in2', 'in3', 'out']:
regfield = entry[fname]
if (fname != 'out' and regfield in svp64_src):
extra_index = svp64_src[regfield]
# ta-daa, we know in1/2/3/out's bit-offset
- entry['sv_%s' % fname] = extra_index
+ if extra_index is not None:
+ entry['sv_%s' % fname] = "Idx"+str(extra_index)
+
+ # TODO: CRs a little tricky, the power_enums.CRInSel is a bit odd.
+ # ignore WHOLE_REG for now
+ cr_in = entry['CR in']
+ extra_index = 'NONE'
+ if cr_in in svp64_src:
+ entry['sv_cr_in'] = "Idx"+str(svp64_src[cr_in])
+ elif cr_in == 'BA_BB':
+ index1 = svp64_src.get('BA', None)
+ index2 = svp64_src.get('BB', None)
+ entry['sv_cr_in'] = "Idx_%d_%d" % (index1, index2)
+
+ # CRout a lot easier. ignore WHOLE_REG for now
+ cr_out = entry['CR out']
+ extra_index = svp64_dest.get(cr_out, None)
+ if extra_index is not None:
+ entry['sv_cr_out'] = 'Idx%d' % extra_index
+
+ # more enum-friendly Ptype names. should have done this in
+ # sv_analysis.py, oh well
+ if entry['SV_Ptype'] == '1P':
+ entry['SV_Ptype'] = 'P1'
+ if entry['SV_Ptype'] == '2P':
+ entry['SV_Ptype'] = 'P2'
return v30b
minor_30 = isa.get_svp64_csv("minor_30.csv")
for entry in minor_30:
print (entry)
+ minor_19 = isa.get_svp64_csv("minor_19.csv")
+ for entry in minor_19:
+ if entry['comment'].startswith('cr'):
+ print (entry)
+ minor_31 = isa.get_svp64_csv("minor_31.csv")
+ for entry in minor_31:
+ print (entry)