add a DIVS function as separate and discrete from floor_div

[soc.git] / src / soc / decoder / pseudo / pywriter.py

diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py
index f6c1ef6a7f9047af16dcd40ee43146e94c75917c..f06d996f388399bb8cd078107bc967f394788bbb 100644 (file)
--- a/src/soc/decoder/pseudo/pywriter.py
+++ b/src/soc/decoder/pseudo/pywriter.py
@@ -20,7 +20,8 @@ header = """\
 
 from soc.decoder.isa.caller import inject, instruction_info
 from soc.decoder.helpers import (EXTS, EXTS64, EXTZ64, ROTL64, ROTL32, MASK,
-                                 ne, eq, gt, ge, lt, le, length)
+                                 ne, eq, gt, ge, lt, le, ltu, gtu, length,
+                                 trunc_divs, trunc_rems, MULS, DIVS, MODS)
 from soc.decoder.selectable_int import SelectableInt
 from soc.decoder.selectable_int import selectconcat as concat
 from soc.decoder.orderedset import OrderedSet
@@ -52,10 +53,10 @@ class PyISAWriter(ISA):
             # go through all instructions
             for page in instrs:
                 d = self.instr[page]
-                print (fname, d.opcode)
+                print ("page", pagename, page, fname, d.opcode)
                 pcode = '\n'.join(d.pcode) + '\n'
                 print (pcode)
-                incl_carry = page == 'fixedshift'
+                incl_carry = pagename == 'fixedshift'
                 pycode, rused = convert_to_python(pcode, d.form, incl_carry)
                 # create list of arguments to call
                 regs = list(rused['read_regs']) + list(rused['uninit_regs'])
@@ -110,6 +111,7 @@ class PyISAWriter(ISA):
         fname = os.path.join(isadir, "all.py")
 
         with open(fname, "w") as f:
+            f.write('# auto-generated by pywriter.py: do not edit or commit\n')
             f.write('from soc.decoder.isa.caller import ISACaller\n')
             for page in self.pages_written:
                 f.write('from soc.decoder.isa.%s import %s\n' % (page, page))