Remove left-over comments.

[soc.git] / src / soc / experiment / alu_fsm.py

diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py
index 001de5c279db0f05eda489b8703ade92bc788b99..3fb1c6cfe595d627506a941f87f5d39ab2bb5079 100644 (file)
--- a/src/soc/experiment/alu_fsm.py
+++ b/src/soc/experiment/alu_fsm.py
@@ -17,12 +17,24 @@ The basic rules are:
 """
 
 from nmigen import Elaboratable, Signal, Module, Cat
-from nmigen.back.pysim import Simulator
 from nmigen.cli import rtlil
-from soc.fu.cr.cr_input_record import CompCROpSubset
 from math import log2
+
 from nmutil.iocontrol import PrevControl, NextControl
 
+from soc.fu.base_input_record import CompOpSubsetBase
+
+from nmutil.gtkw import write_gtkw
+from nmutil.sim_tmp_alternative import (Simulator, is_engine_pysim)
+
+
+class CompFSMOpSubset(CompOpSubsetBase):
+    def __init__(self, name=None):
+        layout = (('sdir', 1),
+                  )
+
+        super().__init__(layout, name=name)
+
 
 class Dummy:
     pass
@@ -38,7 +50,9 @@ class Shifter(Elaboratable):
     *                 On POWER, range is 0 to 63 for 32-bit,
     *                 and 0 to 127 for 64-bit.
     *                 Other values wrap around.
-    * p.data_i.dir:   shift direction (0 = left, 1 = right)
+
+    Operation type
+    * op.sdir:       shift direction (0 = left, 1 = right)
 
     Next port data:
     * n.data_o.data: shifted value
@@ -47,8 +61,7 @@ class Shifter(Elaboratable):
         def __init__(self, width):
             self.data = Signal(width, name="p_data_i")
             self.shift = Signal(width, name="p_shift_i")
-            self.dir = Signal(name="p_dir_i")
-            self.ctx = Dummy() # comply with CompALU API
+            self.ctx = Dummy()  # comply with CompALU API
 
         def _get_data(self):
             return [self.data, self.shift]
@@ -68,7 +81,7 @@ class Shifter(Elaboratable):
         self.n.data_o = Shifter.NextData(width)
 
         # more pieces to make this example class comply with the CompALU API
-        self.op = CompCROpSubset()
+        self.op = CompFSMOpSubset(name="op")
         self.p.data_i.ctx.op = self.op
         self.i = self.p.data_i._get_data()
         self.out = self.n.data_o._get_data()
@@ -146,7 +159,7 @@ class Shifter(Elaboratable):
                     next_count.eq(self.p.data_i.shift),
                 ]
                 # capture the direction bit as well
-                m.d.sync += direction.eq(self.p.data_i.dir)
+                m.d.sync += direction.eq(self.op.sdir)
                 with m.If(self.p.valid_i):
                     # Leave IDLE when data arrives
                     with m.If(next_count == 0):
@@ -174,9 +187,9 @@ class Shifter(Elaboratable):
         return m
 
     def __iter__(self):
+        yield self.op.sdir
         yield self.p.data_i.data
         yield self.p.data_i.shift
-        yield self.p.data_i.dir
         yield self.p.valid_i
         yield self.p.ready_o
         yield self.n.ready_i
@@ -198,6 +211,36 @@ def test_shifter():
     il = rtlil.convert(dut, ports=dut.ports())
     with open("test_shifter.il", "w") as f:
         f.write(il)
+
+    gtkwave_style = {
+        'in': {'color': 'orange'},
+        'out': {'color': 'yellow'},
+    }
+
+    gtkwave_desc = [
+        'clk',
+        {'comment': 'Shifter Demonstration'},
+        ('prev port', [
+            ('op__sdir', 'in'),
+            ('p_data_i[7:0]', 'in'),
+            ('p_shift_i[7:0]', 'in'),
+            ({'submodule': 'p'}, [
+                ('p_valid_i', 'in'),
+                ('p_ready_o', 'out')])]),
+        ('internal', [
+            'fsm_state' if is_engine_pysim() else 'fsm_state[1:0]',
+            'count[3:0]',
+            'shift_reg[7:0]']),
+        ('next port', [
+            ('n_data_o[7:0]', 'out'),
+            ({'submodule': 'n'}, [
+                ('n_valid_o', 'out'),
+                ('n_ready_i', 'in')])])]
+
+    write_gtkw("test_shifter.gtkw", "test_shifter.vcd",
+               gtkwave_desc,  gtkwave_style,
+               module='top.shf', loc=__file__, base='dec')
+
     sim = Simulator(m)
     sim.add_clock(1e-6)
 
@@ -205,7 +248,7 @@ def test_shifter():
         # present input data and assert valid_i
         yield dut.p.data_i.data.eq(data)
         yield dut.p.data_i.shift.eq(shift)
-        yield dut.p.data_i.dir.eq(direction)
+        yield dut.op.sdir.eq(direction)
         yield dut.p.valid_i.eq(1)
         yield
         # wait for p.ready_o to be asserted
@@ -215,7 +258,7 @@ def test_shifter():
         yield dut.p.valid_i.eq(0)
         yield dut.p.data_i.data.eq(0)
         yield dut.p.data_i.shift.eq(0)
-        yield dut.p.data_i.dir.eq(0)
+        yield dut.op.sdir.eq(0)
 
     def receive(expected):
         # signal readiness to receive data
@@ -251,11 +294,7 @@ def test_shifter():
 
     sim.add_sync_process(producer)
     sim.add_sync_process(consumer)
-    sim_writer = sim.write_vcd(
-        "test_shifter.vcd",
-        "test_shifter.gtkw",
-        traces=dut.ports()
-    )
+    sim_writer = sim.write_vcd("test_shifter.vcd")
     with sim_writer:
         sim.run()