"""
from nmigen import Elaboratable, Signal, Module, Cat
-cxxsim = False
-if cxxsim:
- from nmigen.sim.cxxsim import Simulator, Settle
-else:
- from nmigen.back.pysim import Simulator, Settle
from nmigen.cli import rtlil
from math import log2
+
from nmutil.iocontrol import PrevControl, NextControl
from soc.fu.base_input_record import CompOpSubsetBase
-from soc.decoder.power_enums import (MicrOp, Function)
+
+from nmutil.gtkw import write_gtkw
+from nmutil.sim_tmp_alternative import (Simulator, is_engine_pysim)
class CompFSMOpSubset(CompOpSubsetBase):
super().__init__(layout, name=name)
-
class Dummy:
pass
def __init__(self, width):
self.data = Signal(width, name="p_data_i")
self.shift = Signal(width, name="p_shift_i")
- self.ctx = Dummy() # comply with CompALU API
+ self.ctx = Dummy() # comply with CompALU API
def _get_data(self):
return [self.data, self.shift]
il = rtlil.convert(dut, ports=dut.ports())
with open("test_shifter.il", "w") as f:
f.write(il)
+
+ gtkwave_style = {
+ 'in': {'color': 'orange'},
+ 'out': {'color': 'yellow'},
+ }
+
+ gtkwave_desc = [
+ 'clk',
+ {'comment': 'Shifter Demonstration'},
+ ('prev port', [
+ ('op__sdir', 'in'),
+ ('p_data_i[7:0]', 'in'),
+ ('p_shift_i[7:0]', 'in'),
+ ({'submodule': 'p'}, [
+ ('p_valid_i', 'in'),
+ ('p_ready_o', 'out')])]),
+ ('internal', [
+ 'fsm_state' if is_engine_pysim() else 'fsm_state[1:0]',
+ 'count[3:0]',
+ 'shift_reg[7:0]']),
+ ('next port', [
+ ('n_data_o[7:0]', 'out'),
+ ({'submodule': 'n'}, [
+ ('n_valid_o', 'out'),
+ ('n_ready_i', 'in')])])]
+
+ write_gtkw("test_shifter.gtkw", "test_shifter.vcd",
+ gtkwave_desc, gtkwave_style,
+ module='top.shf', loc=__file__, base='dec')
+
sim = Simulator(m)
sim.add_clock(1e-6)
sim.add_sync_process(producer)
sim.add_sync_process(consumer)
- sim_writer = sim.write_vcd(
- "test_shifter.vcd",
- )
+ sim_writer = sim.write_vcd("test_shifter.vcd")
with sim_writer:
sim.run()