Remove left-over comments.

[soc.git] / src / soc / experiment / alu_fsm.py

diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py
index 2cdc7c324855d69f13395caef3362892d4df2631..3fb1c6cfe595d627506a941f87f5d39ab2bb5079 100644 (file)
--- a/src/soc/experiment/alu_fsm.py
+++ b/src/soc/experiment/alu_fsm.py
@@ -17,19 +17,15 @@ The basic rules are:
 """
 
 from nmigen import Elaboratable, Signal, Module, Cat
-cxxsim = False
-if cxxsim:
-    from nmigen.sim.cxxsim import Simulator, Settle
-else:
-    from nmigen.back.pysim import Simulator, Settle
 from nmigen.cli import rtlil
 from math import log2
+
 from nmutil.iocontrol import PrevControl, NextControl
 
 from soc.fu.base_input_record import CompOpSubsetBase
-from soc.decoder.power_enums import (MicrOp, Function)
 
-from vcd.gtkw import GTKWSave, GTKWColor
+from nmutil.gtkw import write_gtkw
+from nmutil.sim_tmp_alternative import (Simulator, is_engine_pysim)
 
 
 class CompFSMOpSubset(CompOpSubsetBase):
@@ -40,7 +36,6 @@ class CompFSMOpSubset(CompOpSubsetBase):
         super().__init__(layout, name=name)
 
 
-
 class Dummy:
     pass
 
@@ -66,7 +61,7 @@ class Shifter(Elaboratable):
         def __init__(self, width):
             self.data = Signal(width, name="p_data_i")
             self.shift = Signal(width, name="p_shift_i")
-            self.ctx = Dummy() # comply with CompALU API
+            self.ctx = Dummy()  # comply with CompALU API
 
         def _get_data(self):
             return [self.data, self.shift]
@@ -205,49 +200,6 @@ class Shifter(Elaboratable):
         return list(self)
 
 
-# Write a formatted GTKWave "save" file
-def write_gtkw(base_name, top_dut_name, loc):
-    # hierarchy path, to prepend to signal names
-    dut = top_dut_name + "."
-    # color styles
-    style_input = GTKWColor.orange
-    style_output = GTKWColor.yellow
-    style_debug = GTKWColor.red
-    with open(base_name + ".gtkw", "wt") as gtkw_file:
-        gtkw = GTKWSave(gtkw_file)
-        gtkw.comment("Auto-generated by " + loc)
-        gtkw.dumpfile(base_name + ".vcd")
-        # set a reasonable zoom level
-        # also, move the marker to an interesting place
-        gtkw.zoom_markers(-22.9, 10500000)
-        gtkw.trace(dut + "clk")
-        # place a comment in the signal names panel
-        gtkw.blank("Shifter Demonstration")
-        with gtkw.group("prev port"):
-            gtkw.trace(dut + "op__sdir", color=style_input)
-            # demonstrates using decimal base (default is hex)
-            gtkw.trace(dut + "p_data_i[7:0]", color=style_input,
-                       datafmt='dec')
-            gtkw.trace(dut + "p_shift_i[7:0]", color=style_input,
-                       datafmt='dec')
-            gtkw.trace(dut + "p_valid_i", color=style_input)
-            gtkw.trace(dut + "p_ready_o", color=style_output)
-        with gtkw.group("debug"):
-            gtkw.blank("Some debug statements")
-            # change the displayed name in the panel
-            gtkw.trace("top.zero", alias='zero delay shift',
-                       color=style_debug)
-        with gtkw.group("internal"):
-            gtkw.trace(dut + "fsm_state")
-            gtkw.trace(dut + "count[3:0]")
-            gtkw.trace(dut + "shift_reg[7:0]", datafmt='dec')
-        with gtkw.group("next port"):
-            gtkw.trace(dut + "n_data_o[7:0]", color=style_output,
-                       datafmt='dec')
-            gtkw.trace(dut + "n_valid_o", color=style_output)
-            gtkw.trace(dut + "n_ready_i", color=style_input)
-
-
 def test_shifter():
     m = Module()
     m.submodules.shf = dut = Shifter(8)
@@ -260,17 +212,38 @@ def test_shifter():
     with open("test_shifter.il", "w") as f:
         f.write(il)
 
-    # Write the GTKWave project file
-    write_gtkw("test_shifter", "top.shf", __file__)
+    gtkwave_style = {
+        'in': {'color': 'orange'},
+        'out': {'color': 'yellow'},
+    }
+
+    gtkwave_desc = [
+        'clk',
+        {'comment': 'Shifter Demonstration'},
+        ('prev port', [
+            ('op__sdir', 'in'),
+            ('p_data_i[7:0]', 'in'),
+            ('p_shift_i[7:0]', 'in'),
+            ({'submodule': 'p'}, [
+                ('p_valid_i', 'in'),
+                ('p_ready_o', 'out')])]),
+        ('internal', [
+            'fsm_state' if is_engine_pysim() else 'fsm_state[1:0]',
+            'count[3:0]',
+            'shift_reg[7:0]']),
+        ('next port', [
+            ('n_data_o[7:0]', 'out'),
+            ({'submodule': 'n'}, [
+                ('n_valid_o', 'out'),
+                ('n_ready_i', 'in')])])]
+
+    write_gtkw("test_shifter.gtkw", "test_shifter.vcd",
+               gtkwave_desc,  gtkwave_style,
+               module='top.shf', loc=__file__, base='dec')
 
     sim = Simulator(m)
     sim.add_clock(1e-6)
 
-    # demonstrates adding extra debug signal traces
-    # they end up in the top module
-    #
-    zero = Signal()  # mark an interesting place
-
     def send(data, shift, direction):
         # present input data and assert valid_i
         yield dut.p.data_i.data.eq(data)
@@ -317,19 +290,11 @@ def test_shifter():
         # 3 << 4 = 48
         yield from receive(48)
         # 21 << 0 = 21
-        # you can look for the rising edge of this signal to quickly
-        # locate this point in the traces
-        yield zero.eq(1)
         yield from receive(21)
-        yield zero.eq(0)
 
     sim.add_sync_process(producer)
     sim.add_sync_process(consumer)
-    sim_writer = sim.write_vcd(
-        "test_shifter.vcd",
-        # include additional signals in the trace dump
-        traces=[zero]
-    )
+    sim_writer = sim.write_vcd("test_shifter.vcd")
     with sim_writer:
         sim.run()