Make all ports the same size, on the test ALU

[soc.git] / src / soc / experiment / alu_hier.py

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index a780dd86357e4c5cb1fc75148d38911b509bf380..76d8e22126d21e06c2da58e774a6befb7504bc34 100644 (file)
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -198,7 +198,7 @@ class ALU(Elaboratable):
         self.a, self.b = i[0], i[1]
         out = []
         out.append(Data(width, name="alu_o"))
-        out.append(Data(3, name="alu_cr"))
+        out.append(Data(width, name="alu_cr"))
         self.out = Array(out)
         self.o = self.out[0]
         self.cr = self.out[1]