tracked down byte-reversal in LDST ISACaller and LDSTCompUnit

[soc.git] / src / soc / experiment / compldst_multi.py

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 4e34a7698eb6987337f64e1a138f2f28f7ff6d28..e464da2a319c46af56aaf001cd7a92ba153a116a 100644 (file)
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -483,7 +483,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
 
         # byte-reverse on LD - yes this is inverted
         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
 
         # byte-reverse on LD - yes this is inverted

-        with m.If(self.oper_i.byte_reverse):
+        with m.If(~self.oper_i.byte_reverse):

             comb += ldd_o.eq(pi.ld.data)  # put data out, straight (as BE)
         with m.Else():
             # byte-reverse the data based on ld/st width (turn it to LE)
             comb += ldd_o.eq(pi.ld.data)  # put data out, straight (as BE)
         with m.Else():
             # byte-reverse the data based on ld/st width (turn it to LE)


@@ -494,7 +494,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         comb += ld_ok.eq(pi.ld.ok)  # ld.ok *closes* (freezes) ld data
 
         # yes this also looks odd (inverted)
         comb += ld_ok.eq(pi.ld.ok)  # ld.ok *closes* (freezes) ld data
 
         # yes this also looks odd (inverted)

-        with m.If(self.oper_i.byte_reverse):
+        with m.If(~self.oper_i.byte_reverse):

             comb += pi.st.data.eq(srl[2])  # 3rd operand latch
         with m.Else():
             # byte-reverse the data based on width
             comb += pi.st.data.eq(srl[2])  # 3rd operand latch
         with m.Else():
             # byte-reverse the data based on width