looked in soc.vhdl in microwatt and the parameters are 64 cache

[soc.git] / src / soc / experiment / icache.py

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 8010bf2eab37718fd4b1c9533434dccad2d317bb..3f37b5bfa0c271b8c28fd7fd218f8ce862b5022a 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -72,9 +72,9 @@ LINE_SIZE      = 64
 # ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
 ROW_SIZE       = WB_DATA_BITS // 8
 # Number of lines in a set
-NUM_LINES      = 32
+NUM_LINES      = 64
 # Number of ways
-NUM_WAYS       = 4
+NUM_WAYS       = 2
 # L1 ITLB number of entries (direct mapped)
 TLB_SIZE       = 64
 # L1 ITLB log_2(page_size)